SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 472

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

25.1.16.9
Name:
Address:
Access:
Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC.
Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
This register can only be written if the WPEN bit is cleared in
• DIVA: Divider
• PLLACOUNT: PLLA Counter
Specifies the number of Slow Clock cycles x8 before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• MULA: PLLA Multiplier
0 = The PLLA is deactivated.
1 up to 36 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA + 1.
• ONE: Must Be Set to 1
Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
472
472
DIVA
0
1
2 - 255
31
23
15
–
–
7
SAM3S8/SD8
SAM3S8/SD8
PMC Clock Generator PLLA Register
CKGR_PLLAR
0x400E0428
30
22
14
Read-write
–
–
6
Divider Selected
Divider output is 0
Divider is bypassed (DIVA=1)
Divider output is DIVA
ONE
29
21
13
5
28
20
12
–
4
MULA
DIVA
“PMC Write Protect Mode Register”
27
19
11
–
3
PLLACOUNT
26
18
10
2
MULA
.
25
17
9
1
11090A–ATARM–10-Feb-12
11090A–ATARM–10-Feb-12
24
16
8
0