AD9642 Analog Devices, AD9642 Datasheet - Page 6

• Manufacturer Part Number: AD9642
• Description: 14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9642

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: LVDS
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9642
SWITCHING SPECIFICATIONS
Table 4.
Parameter
CLOCK INPUT PARAMETERS
DATA OUTPUT PARAMETERS
1
Timing Diagram
Conversion rate is the clock rate after the divider.
Data Propagation Delay (t
DCO Propagation Delay (t
DCO-to-Data Skew (t
Out-of-Range Recovery Time
Input Clock Rate
Conversion Rate
CLK Period—Divide-by-1 Mode (t
CLK Pulse Width High (t
Aperture Delay (t
Aperture Uncertainty (Jitter, t
Pipeline Delay (Latency)
Wake-Up Time (from Standby)
Wake-Up Time (from Power-Down)
EVEN/ODD
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode Through
Divide-by-8 Mode
D12±/D13±
DCO–
DCO+
CLK+
CLK–
D0±/D1±
VIN
(MSB)
(LSB)
1
A
)
SKEW
CH
)
)
DCO
PD
)
)
J
)
CLK
N – 1
)
t
CH
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
t
A
t
t
DCO
PD
N
Min
40
5.8
2.61
2.76
0.8
4.1
4.7
0.3
Figure 2. LVDS Data Output Timing
N – 10
N – 10
t
D12
AD9642-170
CLK
D0
t
SKEW
Rev. 0 | Page 6 of 28
Typ
2.9
2.9
1.0
0.1
4.7
5.3
0.5
10
10
100
3
N – 10
N – 10
D13
N + 1
D1
Max
625
170
3.19
3.05
5.2
5.8
0.7
N – 9
N – 9
D12
D0
Min
40
4.8
2.28
0.8
4.1
4.7
0.3
2.16
N – 9
N – 9
N + 2
D13
D1
AD9642-210
Typ
2.4
2.4
1.0
0.1
4.7
5.3
0.5
10
10
100
3
N – 8
N – 8
D12
D0
N + 3
N – 8
N – 8
D13
Max
625
210
2.64
2.52
5.2
5.8
0.7
D1
N – 7
N – 7
D12
D0
Min
40
4
1.8
1.9
0.8
4.1
4.7
0.3
AD9642-250
N + 4
N – 7
N – 7
D12
D1
Typ
2.0
2.0
1.0
0.1
4.7
5.3
0.5
10
10
100
3
N – 6
N – 6
D12
D0
Max
625
250
2.2
2.1
5.2
5.8
0.7
N + 5
Unit
MHz
MSPS
ns
ns
ns
ns
ns
ps rms
ns
ns
ns
Cycles
μs
μs
Cycles