AD9642 Analog Devices, AD9642 Datasheet - Page 9

• Manufacturer Part Number: AD9642
• Description: 14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9642

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: LVDS
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions
Pin No.
ADC Power Supplies
ADC Analog
Digital Outputs
SPI Control
8, 17
3, 27, 28, 31, 32
0
25
30
29
26
1
2
5
4
7
6
10
9
12
11
14
13
16
15
19
18
21
20
23
22
24
Mnemonic
DRVDD
AVDD
AGND,
Exposed Paddle
DNC
VIN+
VIN−
VCM
CLK+
CLK−
D0+/D1+ (LSB)
D0−/D1− (LSB)
D2+/D3+
D2−/D3−
D4+/D5+
D4−/D5−
D6+/D7+
D6−/D7−
D8+/D9+
D8−/D9−
D10+/D11+
D10−/D11−
D12+/D13+ (MSB)
D12−/D13− (MSB)
DCO+
DCO−
SCLK
SDIO
CSB
D0+/D1+ (LSB)
D0–/D1– (LSB)
NOTES
1. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE
2. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
Type
Supply
Supply
Ground
Input
Input
Output
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input/output
Input
PACKAGE PROVIDES THE ANALOG GROUND FOR THE
PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO
GROUND FOR PROPER OPERATION.
D2–/D3–
D2+/D3+
DRVDD
AVDD
CLK+
CLK–
Figure 3. LFCSP Pin Configuration (Top View)
1
2
3
4
5
6
7
8
INTERLEAVED
Rev. 0 | Page 9 of 28
(Not to Scale)
Description
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. The exposed thermal paddle on the bottom of the package provides
the analog ground for the part. This exposed paddle must be connected to ground for
proper operation.
Do Not Connect. Do not connect to this pin.
Differential Analog Input Pin (+).
Differential Analog Input Pin (−).
Common-Mode Level Bias Output for Analog Inputs.
to ground using a 0.1 μF capacitor.
ADC Clock Input—True.
ADC Clock Input—Complement.
DDR LVDS Output Data 0/1—True.
DDR LVDS Output Data 0/1—Complement.
DDR LVDS Output Data 2/3—True.
DDR LVDS Output Data 2/3—Complement.
DDR LVDS Output Data 4/5—True.
DDR LVDS Output Data 4/5—Complement.
DDR LVDS Output Data 6/7—True.
DDR LVDS Output Data 6/7—Complement.
DDR LVDS Output Data 8/9—True.
DDR LVDS Output Data 8/9—Complement.
DDR LVDS Output Data 10/11—True.
DDR LVDS Output Data 10/11—Complement.
DDR LVDS Output Data 12/13—True.
DDR LVDS Output Data 12/13—Complement.
LVDS Data Clock Output—True.
LVDS Data Clock Output—Complement.
SPI Serial Clock.
SPI Serial Data I/O.
SPI Chip Select (Active Low).
AD9642
TOP VIEW
LVDS
24 CSB
23 SCLK
22 SDIO
21 DCO+
20 DCO–
19 D12+/D13+ (MSB)
18 D12–/D13– (MSB)
17 DRVDD
This pin should be decoupled
AD9642