AD9643 Analog Devices, AD9643 Datasheet - Page 14

• Manufacturer Part Number: AD9643
• Description: 14-Bit, 170/210/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9643

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 250MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9643
Table 9. Pin Function Descriptions for Channel Multiplexed (Even/Odd) LVDS Mode
Pin No.
ADC Power Supplies
ADC Analog
Digital Input
10, 19, 28, 37
49, 50, 53, 54, 59, 60, 63, 64
4, 5
0
51
52
62
61
55
56
58
57
1
2
3
(LSB) B D0–/D1–
(LSB) B D0+/D1+
Figure 5. LFCSP Channel Multiplexed (Even/Odd) LVDS Pin Configuration (Top View)
INDICATOR
B D2–/D3–
B D2+/D3+
B D4–/D5–
B D4+/D5+
B D6–/D7–
B D6+/D7+
Mnemonic
DRVDD
AVDD
DNC
AGND,
Exposed Paddle
VIN+A
VIN−A
VIN+B
VIN−B
DNC
DNC
DNC
VCM
CLK+
CLK−
SYNC
DRVDD
SYNC
CLK+
CLK–
PIN 1
DNC
DNC
DNC
DNC
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE
PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART.
THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR
PROPER OPERATION.
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Type
Supply
Supply
Input
Input
Input
Input
Input
Ground
Output
Input
Input
Rev. B | Page 14 of 36
MULTIPLEXED
(Not to Scale)
(EVEN/ODD)
AD9643
CHANNEL
TOP VIEW
LVDS
Description
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Do Not Connect. Do not connect to this pin.
Analog Ground. The exposed thermal paddle on the bottom of
the package provides the analog ground for the part. This
exposed paddle must be connected to ground for proper
operation.
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Common-Mode Level Bias Output for Analog Inputs. This pin
should be decoupled to ground using a 0.1 μF capacitor.
ADC Clock Input—True.
ADC Clock Input—Complement.
Digital Synchronization Pin. Slave mode only.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OEB
CSB
SCLK
SDIO
OR+
OR–
A D12+/D13+ (MSB)
A D12–/D13– (MSB)
A D10+/D11+
A D10–/D11–
DRVDD
A D8+/D9+
A D8–/D9–
A D6+/D7+
A D6–/D7–
Data Sheet