AD9643 Analog Devices, AD9643 Datasheet - Page 32

• Manufacturer Part Number: AD9643
• Description: 14-Bit, 170/210/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9643

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 250MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9643
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 14 are not currently supported for this device.
Table 14. Memory Map Registers
Addr
(Hex)
Chip Configuration Registers
0x00
0x01
0x02
Channel Index and Transfer Registers
0x05
0xFF
ADC Functions
0x08
0x09
0x0B
Register
Name
SPI port
configuration
(global)
Chip ID
(global)
Chip grade
(global)
Channel index
(global)
Transfer
(global)
Power modes
(local)
Global clock
(global)
Clock divide
(global)
1
Bit 7
(MSB)
0
Open
Open
Open
Open
Open
Open
Bit 6
LSB first
Open
Open
Open
Open
Open
Open
Bit 5
Soft reset
Open
Open
External
power-
down pin
function
(local)
0 = power-
down
1 = standby
Open
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
Speed grade ID
00 = 250 MSPS
01 = 210 MSPS
11 = 170 MSPS
Bit 4
1
Open
Open
Open
Open
Rev. B | Page 32 of 36
8-bit chip ID[7:0]
(AD9643 = 0x82)
(default)
Bit 3
1
Open
Open
Open
Open
Open
Bit 2
Soft reset
Open
Open
Open
Open
Open
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
LSB first
Open
Open
Bit 1
ADC B
(default)
Open
Internal power-down mode
(local)
00 = normal operation
01 = full power-down
10 = standby
11 = reserved
Bit 0
(LSB)
0
Open
ADC A
(default)
Transfer
Duty cycle
stabilizer
(default)
Default
Value
(Hex)
0x18
0x82
0x03
0x00
0x00
0x01
0x00
Data Sheet
Default
Notes/
Comments
The nibbles
are mirrored
so that LSB
first mode
or MSB first
mode
registers
correctly,
regardless
of shift
mode.
Read only.
Speed
grade ID
used to
differentiate
devices;
read only.
Bits are
set to
determine
which
device on
the chip
receives
the next
write
command;
applies to
local
registers
only.
Synchro-
nously
transfers
data from
the master
shift register
to the slave.
Determines
various
generic
modes of
chip
operation.
Clock
divide
values
other than
000 auto-
matically
cause the
duty cycle
stabilizer to
become
active.