AD9961 Analog Devices, AD9961 Datasheet - Page 25

• Manufacturer Part Number: AD9961
• Description: 10-/12-Bit, Low Power, Broadband MxFE
• Manufacturer: Analog Devices

Specifications of AD9961

• Resolution (bits): 10bit
• Throughput Rate: 100MSPS
• # Chan: 2
• Supply V: Multi(+1.8Anlg, +1.8Dig),Multi(+1.8Anlg, +3.3Dig) ,Single(+1.8),Single(+3.3)
• Sample Rate: 100MSPS
• Adc Bits X #adcs-speed: 10x2-100 MHz
• Dac Bits X #dacs-clkspeed: 10x2-170 MHz
• Pkg Type: CSP
• Primary Application: Broadband Wireless

Register Name
Tx Data Interface
Rx Data Interface
Register
Address
0x31
0x32
Bit(s)
2
1
0
7
6
5:4
3
2
1
0
7
6
5:4
Parameter
SRRC_BP
TXCLK_EN
RXCLK_EN
TX_SDR
TXCKO_INV
TXCLK_MD[1:0]
TXCKI_INV
TXIQ_HILO
TX_IFIRST
TX_BNRY
RX_SDR
Unused
RXCLK_MD[1:0]
Rev. 0 | Page 25 of 60
Function
1: bypass 2× SRRC interpolation filter (SRRC).
The filter chain is SRRC→INT0→INT1.
If SRRC filter is enabled, the other two filters are enabled too.
1: enables data clocks for transmit path.
1: enables data clocks for receive path.
0: chooses DDR clocking mode. Tx data is driven out on both edges of
the TXCLK signal.
1: chooses bus rate clocking mode. Tx data is driven out on one edge of
the TXCLK signal.
This signal inverts the phase of the transmit path output clock signal.
0: transmit path data transitions on the positive edge of the TXCLK signal.
1: transmit path data transitions on the positive edge of the TXCLK signal.
Controls the mode of the TXCLK pin. The TXCLK pin can be configured as
an input or an output. When configured as an output, it can have two
possible sources, the internal TXCLK signal or the DLL output signal.
00: disabled.
01: the TXCLK pin is configured as an input.
10: the TXCLK pin is configured as an output. The source signal is the
transmit path clock signal.
11: the TXCLK pin is configured as an output. The source signal is the DLL
output signal.
Note that the TXCLK signal may appear on either the TXCLK pin or the
TRXCLK pin, depending on the mode of the device. In Half-Duplex 1-
Clock mode, this signal is present on the TRXCLK pin when TX is active. In
Half-Duplex 2-Clock mode and Full-Duplex mode, this signal is present
on the TXCLK pin.
Selects which edge of the TXCLK signal samples the transmit path data.
0: TXPCLK negative edge latches transmit path data.
1: TXPCLK positive edge latches transmit path data.
Data appears on the TXD bus sequentially but is loaded into the transmit
path in pairs. TXIQ_HILO selects how the TXIQ signal marks each data
pair.
0: each data pair is marked by TXIQ being low then high.
1: each data pair is marked by TXIQ being high then low.
This bit sets the data pairing order of the I and Q samples on transmit
path.
0: selects that Q is first, followed by I.
1: selects that I is first, followed by Q.
This bit selects the data format of the transmit path data.
0: selects twos complement.
1: selects straight binary.
0: chooses DDR clocking mode. Rx data is driven out on both edges of
the TRXCLK signal.
1: chooses bus rate clocking mode. Rx data is driven out on one edge of
the TRXCLK signal.
This sets the way the internal RXCLK signal in the chip is driven.
00: disabled.
01: disabled.
10: RXCLK is driven by internal Rx path clock.
AD9961/AD9963