AD9961 Analog Devices, AD9961 Datasheet - Page 45

• Manufacturer Part Number: AD9961
• Description: 10-/12-Bit, Low Power, Broadband MxFE
• Manufacturer: Analog Devices

Specifications of AD9961

• Resolution (bits): 10bit
• Throughput Rate: 100MSPS
• # Chan: 2
• Supply V: Multi(+1.8Anlg, +1.8Dig),Multi(+1.8Anlg, +3.3Dig) ,Single(+1.8),Single(+3.3)
• Sample Rate: 100MSPS
• Adc Bits X #adcs-speed: 10x2-100 MHz
• Dac Bits X #dacs-clkspeed: 10x2-170 MHz
• Pkg Type: CSP
• Primary Application: Broadband Wireless

DEVICE CLOCKING
CLOCK DISTRIBUTION
The clock distribution diagram shown in Figure 65 gives an
overview of the clocking options for each of the data converters.
The receive path ADCs and the transmit path DACs can be
clocked directly from the CLKP/CLKN inputs or from the
output of the on-chip DLL. The auxiliary ADC sampling clock
is always a divided down version of the input clock. The
auxiliary DACs are updated synchronously with the serial port
clock and have no relationship with the CLKP/CLKN inputs.
The best data converter performance is realized when a low
jitter clock source drives the CLKP/CLKN inputs, and this
signal is used directly (or through the on-chip divider) as the
data converter sampling clocks. The ADC and DAC sampling
clocks are independently selected to be derived from either the
CLKP/CLKN input or from the DLL output, DLLCLK. Using
DLLCLK as the data converter sampling clock signal may
degrade the noise and SFDR performance of the converters.
More information is given in the Clock Multiplication Using the
DLL section.
The receive path ADC has a duty cycle stabilizer (DCS) to help
make the ADC performance insensitive to changes in the input
CLKP
CLKN
CLK_PD
÷ADCDIV
÷AUXDIV
DLL
M
N
Figure 65. Clock Distribution Diagram
DLLCLK
Rev. 0 | Page 45 of 60
ADCCLKSEL
DACCLKSEL
0
1
1
0
÷DLLDIV
clock duty cycle. The DCS can be bypassed. Recommendations
for using the DCS can be found in the Clock Duty Cycle
Considerations section.
The ADC clock divider and the DLL clock multiplication
supports a variety of ratios between the receive path ADC
sampling clock and the transmit path DAC sampling clock.
Table 21 details the specific values the device supports and
which register bits are require configuration.
Table 21. Clock Tree Configuration Variables
Variable
DCS_BP
ADCDIV
ADCCLKSEL
DACCLKSEL
N
M
DLLDIV
AUXDIV
DCS
DCS_BP
1
0
EXTDLLCLK
ADCCLK
DACCLK
AUXCLK
Values
0 or1
1, 2, 4
0 or 1
0 or 1
1 to 6, 8
1, 2, 3,…, 32
1, 2, 4
2J, J = 1 to 8
AUXADC
ADC
DAC
AD9961/AD9963
Register
0x66
0x66
0x71
0x71
0x71
0x72
0x72
0x7A
Address
Bit(s)
2
[1:0]
7
6
[3:0]
[4:0]
[6:5]
[2:0]