AD9961 Analog Devices, AD9961 Datasheet - Page 37

• Manufacturer Part Number: AD9961
• Description: 10-/12-Bit, Low Power, Broadband MxFE
• Manufacturer: Analog Devices

Specifications of AD9961

• Resolution (bits): 10bit
• Throughput Rate: 100MSPS
• # Chan: 2
• Supply V: Multi(+1.8Anlg, +1.8Dig),Multi(+1.8Anlg, +3.3Dig) ,Single(+1.8),Single(+3.3)
• Sample Rate: 100MSPS
• Adc Bits X #adcs-speed: 10x2-100 MHz
• Dac Bits X #dacs-clkspeed: 10x2-170 MHz
• Pkg Type: CSP
• Primary Application: Broadband Wireless

The filter coefficients of the 2× decimation low-pass are shown
in Table 16.
Table 16.
Lower Coefficient
H(1)
H(3)
H(5)
H(7)
H(9)
H(11)
H(13)
H(15)
H(17)
H(19)
H(21)
H(22)
Figure 46. Pass-Band Response of the Rx Path Decimation Filter
–10
–20
–30
–40
–50
–60
–70
–80
0
NORMALIZED FREQUENCY (Relative to f
Upper Coefficient
H(43)
H(41)
H(39)
H(37)
H(35)
H(33)
H(31)
H(29)
H(27)
H(25)
H(23)
Value
12
−32
72
−140
252
−422
682
−1086
1778
−3284
10364
16384
DAC
)
Rev. 0 | Page 37 of 60
ADC Digital Offset Adjustment
The Rx paths also have individual digital offsets that can be
applied to the data captured by the ADCs. The offset is a 6-bit
digital value that is added directly to the LSBs of the ADC
output data. The offset values are configured by first addressing
the ADC by setting the appropriate address in Register 0x05,
then writing the desired offset (in LSBs) into Register 0x10. For
example, to set offsets of +6 and −2 to the I and Q channels
respectively, the register write sequence is:
1.
2.
3.
4.
5.
6.
Write 0x01 into Register 0x05. This addresses the I channel
ADC.
Write 0x06 into Register 0x10. This sets the IADC_Offset
value to +6 LSBs.
Write 0x02 into Register 0x05. This addresses the Q
channel ADC.
Write 0xFE into Register 0x10. This sets the QADC_Offset
value to −2 LSBs.
Write 0x01 into Register 0xFF. This updates the data path
registers and applies the offset to the data.
Write 0x00 into Register 0x05. This returns the SPI to the
normal addressing mode.
AD9961/AD9963