AD9212 Analog Devices, AD9212 Datasheet
AD9212
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AD9212 Summary of contents
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... Optical networking Test equipment GENERAL DESCRIPTION The AD9212 is an octal, 10-bit, 40 MSPS/65 MSPS ADC with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. Operating at a conversion rate MSPS optimized for outstanding dynamic performance and low power in applications where a small package size is critical ...
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... AD9212 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 AC Specifications .......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 Timing Diagrams .......................................................................... 8 Absolute Maximum Ratings .......................................................... 10 Thermal Impedance ................................................................... 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Equivalent Circuits ......................................................................... 13 Typical Performance Characteristics ........................................... 15 Theory of Operation ...................................................................... 20 Analog Input Considerations .................................................... 20 ...
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... Changes to Default Operation and Jumper Selection Settings Section .............................................................................................. 37 Changes to Alternative Analog Input Drive Configuration Section .............................................................................................. 38 Changes to Figure 73 ...................................................................... 38 Change to Figure 75 ........................................................................ 40 Changes to Figure 76 ...................................................................... 41 Changes to Figure 80 ...................................................................... 45 Changes to Table 17 ........................................................................ 52 Updated Outline Dimensions ........................................................ 55 Changes to Ordering Guide ........................................................... 55 10/06—Revision 0: Initial Version Rev Page AD9212 ...
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... Full 1.7 1.8 1.9 Full 252 260 Full 49.5 53 Full 542 560 Full 3 11 Full 83 Full −90 Full −90 Rev Page Data Sheet AD9212-65 Min Typ Max Unit 10 Bits Guaranteed ±1.5 ±8 mV ±3 ±8 mV ±3.2 ±4 ±0.4 ±0 ±0.3 ±0.65 LSB ±0.4 ±1 LSB ± ...
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... Full 79 25°C Full 74 Full −87 Full −85 Full −79 25°C Full −74 Full −90 Full −85 Full −85 Full −85 25°C 80.0 25°C 77.0 Rev Page AD9212 AD9212-65 Max Min Typ Max Unit 60.8 dB 60.8 dB 58.5 60.8 dB 60.7 dB 60.7 dB 60.6 dB 57.0 60.5 dB 60.4 dB 9.81 Bits 9.81 Bits 9.43 9.81 Bits 9 ...
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... Full 1.79 Full 0.05 LVDS Full 247 454 Full 1.125 1.375 Offset binary LVDS Full 150 250 Full 1.10 1.30 Offset binary Rev Page Data Sheet AD9212-65 Min Typ Max Unit CMOS/LVDS/LVPECL 250 mV p-p 1 kΩ 1.5 pF 1.2 3 kΩ 0.5 pF 1.2 3 kΩ ...
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... SAMPLE (t /20) − 300 (t /20) (t /20) + 300 SAMPLE SAMPLE SAMPLE (t /20) − 300 (t /20) (t /20) + 300 SAMPLE SAMPLE SAMPLE ±50 ±200 600 375 8 750 <1 1 AD9212 Unit MSPS MSPS μs CLK cycles ps ps rms CLK cycles ...
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... AD9212 TIMING DIAGRAMS N – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – x ...
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... – – – – – – – 9 Figure 4. 10-Bit Data Serial Stream, LSB First Rev Page AD9212 LSB – – – – – – ...
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... AD9212 ABSOLUTE MAXIMUM RATINGS Table 5. With Parameter Respect To ELECTRICAL AVDD AGND DRVDD DRGND AGND DRGND AVDD DRVDD Digital Outputs DRGND ( − x, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− AGND VIN + x, VIN − x AGND SDIO/ODM AGND PDWN, SCLK/DTP, CSB ...
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... Frame Clock Digital Output Complement Frame Clock Digital Output True ADC D Digital Output Complement ADC D Digital Output True ADC C Digital Output Complement ADC C Digital Output True ADC B Digital Output Complement Rev Page AD9212 48 AVDD 47 VIN + B 46 VIN – AVDD 44 VIN – ...
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... AD9212 Pin No. Mnemonic − SCLK/DTP 39 SDIO/ODM 40 CSB 41 PDWN 43 VIN + A 44 VIN − VIN − VIN + B 49 VIN + C 50 VIN − VIN − VIN + D 54 RBIAS 55 SENSE 56 VREF 57 REFB 58 REFT 60 VIN + E 61 VIN − VIN − ...
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... Figure 8. Equivalent SDIO/ODM Input Circuit 1.25V SCLK/DTP OR PDWN Rev Page DRVDD – DRGND Figure 9. Equivalent Digital Output Circuit 1kΩ 30kΩ Figure 10. Equivalent SCLK/DTP or PDWN Input Circuit 100Ω RBIAS Figure 11. Equivalent RBIAS Circuit AD9212 ...
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... AD9212 AVDD 70kΩ 1kΩ CSB Figure 12. Equivalent CSB Input Circuit 1kΩ SENSE Figure 13. Equivalent SENSE Circuit VREF Figure 14. Equivalent VREF Circuit Rev Page Data Sheet 6kΩ ...
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... FREQUENCY (MHz MHz, AD9212- AIN = –0.5dBFS SNR = 60.25dB ENOB = 9.66 SFDR = 72.45dBc FREQUENCY (MHz MHz, AD9212- AIN = –0.5dBFS SNR = 60.08dB ENOB = 9.61 SFDR = 71.68dBc FREQUENCY (MHz) = 120 MHz, AD9212-65 IN AD9212 30 30 ...
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... MHz, AD9212-65 SAMPLE SFDR 40 70dB REFERENCE 30 SNR –60 –50 –40 –30 –20 ANALOG INPUT LEVEL (dBFS) = 10.3 MHz, AD9212-40 IN 100 SFDR 40 30 70dB REFERENCE SNR –60 –50 –40 –30 –20 ANALOG INPUT LEVEL (dBFS) ...
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... MHz, AD9212-65 IN2 0 AIN1 AND AIN2 = –7dBFS SFDR = 72.5dB IMD2 = 77.14dBc IMD3 = 72.55dBc –20 –40 –60 – FREQUENCY (MHz) Figure 32. Two-Tone 32k FFT with MHz and IN1 MHz, AD9212- 65 IN2 AD9212 MHz, IN2 30 30 ...
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... MHz, AD9212-65 IN 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 200 400 600 CODE Figure 37. DNL 2.3 MHz, AD9212-65 IN –30 –35 –40 –45 –50 –55 –60 –65 – FREQUENCY (MHz) Figure 38. CMRR vs. Frequency, AD9212-65 Data Sheet 800 1000 800 1000 35 40 ...
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... LSB rms –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 – Figure 41. Full Power Bandwidth vs. Frequency, AD9212- Rev Page AD9212 –3dB BANDWIDTH = 325MHz 50 100 150 200 250 300 350 400 450 FREQUENCY (MHz) 500 ...
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... Front-End for Wideband A/D for more information. In general, the precise values depend on the application. The analog inputs of the AD9212 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide this bias externally. Setting the device so that V recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 45 and Figure 46 ...
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... Figure 44. SNR/SFDR vs. Common-Mode Voltage 19.7 MHz, AD9212- 1.2 1.5 0 1.2 1.5 0.3 Rev Page SFDR SNR 0.6 0.9 1.2 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 45. SNR/SFDR vs. Common-Mode Voltage 2.3 MHz, AD9212-65 IN SFDR SNR 0.6 0.9 1.2 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 46. SNR/SFDR vs. Common-Mode Voltage MHz, AD9212-65 IN AD9212 1.5 1.5 ...
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... In the case of the AD9212, the largest input span available p-p. Differential Input Configurations There are several ways to drive the AD9212 either actively or passively; however, optimum performance is achieved by driving the analog input differentially. For example, using the ...
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... This allows a wide range of clock input duty cycles without affecting the performance of the AD9212. When the DCS is on, noise and distortion perfor- mance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, 0.1µ ...
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... Figure 56). The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9212. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise ...
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... An example of the FCO and data stream when the AD9212 is used with traces of proper length and position is shown in Figure 59. CH1 500mV/DIV = FCO ...
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... AD9212 500 EYE: ALL BITS 400 300 200 100 0 –100 –200 –300 –400 –500 –1.5ns –1.0ns –0.5ns 0ns 0.5ns –150ps –100ps –50ps 0ps 50ps Figure 60. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths ...
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... Data Sheet Two output clocks are provided to assist in capturing data from the AD9212. The DCO is used to clock the output data and is equal to five times the sample clock (CLK) rate. Data is clocked out of the AD9212 and must be captured on the rising and Table 9. Flexible Output Test Modes ...
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... Section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value must be a specific value instead of all 1s (see Table 10 for the initial values) and the AD9212 inverts the bit stream with relation to the ITU standard. Table 10. PN Sequence Initial ...
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... Voltage Reference A stable, accurate 0.5 V voltage reference is built into the AD9212. This is gained up internally by a factor of 2, setting VREF to 1.0 V, which results in a full-scale differential input span p-p. VREF is set internally by default; however, the VREF pin can be driven externally with a 1.0 V reference to improve accuracy ...
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... AD9212 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift charac- teristics. Figure 66 shows the typical drift characteristics of the internal reference mode. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. The external reference is loaded with an equivalent 6 kΩ ...
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... If multiple SDIO pins share a common connection, care should be taken to ensure that proper V load for each AD9212, Figure 67 shows the number of SDIO pins that can be connected together and the resulting V This interface is flexible enough to be controlled by either serial ...
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... AD9212 CSB SCLK DON’T CARE R A12 SDIO DON’T CARE Table 15. Serial Timing Definitions Parameter Timing (Minimum, ns CLK EN_SDIO t 10 DIS_SDIO 1.800 1.795 1.790 1.785 1 ...
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... Addresses that have values marked as 0 should be considered reserved and have 0 written to their registers during power-up. DEFAULT VALUES When the AD9212 comes out of a reset, critical registers are preloaded with default values. These values are indicated in Table 16, where an X refers to an undefined feature. ...
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... Bit 5 Bit 4 Bit 3 Bit 2 Soft 1 1 Soft reset reset off 0 = off (default) (default) 10-bit Chip ID Bits [7:0] (AD9212 = 0x08), (default Data Data Channel Channel (default) (default off 0 = off Clock Clock ...
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... Rev Page AD9212 Default (LSB) Value Notes/ Bit 1 Bit 0 (Hex) Comments 00 = offset binary 0x00 Configures the (default) outputs and the 01 = twos complement format of the data. ...
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... AD9212 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9212 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD9212 recommended that two separate 1 ...
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... Figure 74 to Figure 78). Figure 70 shows the typical bench characterization setup used to evaluate the ac performance of the AD9212 critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter ...
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... AD9212 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9212 Rev. A evaluation board. Power: Connect the switching power supply that is provided with the evaluation kit between a rated 100 240 V ac wall outlet and P701. ...
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... MHz, Two-Pole Low-Pass Filter Applied to the AD8334 Outputs (Analog Input Signal = −1.03 dBFS, SNR = 56.75 dBc, SFDR = 64.4 dBc) Rev Page 680nH 68pF 680nH 65MSPS SAMPLE AIN = 3.5MHz –20 AD8334 = MAX GAIN SETTING –40 –60 –80 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY (MHz) Figure 73. AD9212 FFT Example Results Using AD9212 ...
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... AD9212 Figure 74. Evaluation Board Schematic, DUT Analog Inputs Rev Page Data Sheet 05968-072 ...
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... Data Sheet Figure 75. Evaluation Board Schematic, DUT Analog Inputs (Continued) Rev Page AD9212 05968-073 ...
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... AD9212 49 VIN_C VIN+C 50 VIN−C VIN_C 51 AVDD AVDD_DUT 52 VIN−D VIN_D R301 53 VIN_D VIN+D 10kΩ 54 RBIAS 55 VSENSE_DUT SENSE 56 VREF VREF_DUT 57 REFB 58 REFT 59 AVDD_DUT AVDD 60 VIN_E VIN+E 61 VIN−E VIN_E 62 AVDD_DUT AVDD 63 VIN−F VIN_F 64 VIN_F VIN+F 0 SLUG Figure 76. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface ...
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... Data Sheet GND RSET S10 6 VREF Figure 77. Evaluation Board Schematic, Clock Circuitry Rev Page AD9212 05968-075 ...
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... AD9212 C510 C509 10µF 0.1µF AVDD_5V R505 10kΩ AVDD_5V C505 0.1µF R503 274Ω C502 0.018µF 0.1µF C501 AVDD_5V CW GND VG12 Variable Gain Circuit (0−1.0V DC) VG12 External Variable Gain Drive Figure 78. Evaluation Board Schematic, Optional DUT Analog Input Drive ...
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... LMD4 20 R609 274Ω INH4 19 COM4 18 COM3 17 C627 0.018µF C626 22pF L604 120nH 0.1µF C625 R608 274Ω C621 0.018µF C620 22pF L603 120nH 0.1µF C619 AVDD_5V CW GND VG78 Variable Gain Circuit (0−1.0V DC) VG78 External Variable Gain Drive AD9212 ...
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... AD9212 CR702 GREEN R709 0Ω SDO_CHA 0Ω R708 SDI_CHA R707 0Ω SCLK_CHA R706 0Ω CSB1_CHA 2 Figure 80. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry C702 C703 0.1µF 0.1µF PICVCC 1 2 PICVCC GP1 3 4 GP1 GP0 5 6 GP0 MCLR/GP3 8 7 MCLR/GP3 ...
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... Data Sheet Figure 81. Evaluation Board Layout, Primary Side Rev Page AD9212 ...
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... AD9212 Figure 82. Evaluation Board Layout, Ground Plane Rev Page Data Sheet ...
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... Data Sheet Figure 83. Evaluation Board Layout, Power Plane Rev Page AD9212 ...
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... AD9212 Figure 84. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page Data Sheet ...
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... X5R Capacitor 603 4.7 μF, ceramic, X5R, 6.3 V, 10% tol Capacitor 402 1000 pF, ceramic, X7R 10% tol Capacitor 402 0.018 μF, ceramic, X7R 10% tol Rev Page AD9212 Manufacturer Part Number Manufacturer Murata GRM155R71C104KA88D Murata GRM1555C1H2R20CZ01D Murata GRM219R60J106KE19D Murata GRM188R60J475KE19D Murata GRM155R71H102KA01D ...
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... AD9212 Qty per Reference Item Board Designator 8 8 C503, C514, C520, C526, C603, C614, C620, C626 9 1 C704 10 9 C307, C714, C715, C716, C717, C719, C720, C721, C722 11 16 C540, C541, C544, C545, C548, C549, C552, C553, C640, C641, C644, C645, ...
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... W, 5% tol Resistor 402 64.9 Ω, 1/ tol Resistor 603 0 Ω, 1/ tol Resistor 402 1 kΩ, 1/ tol Resistor 402 33 Ω, 1/ tol Rev Page AD9212 Manufacturer Manufacturer Part Number NIC NRC04Z0TRF Components Corp. Valpey Fisher VFAC3-BHL-65MHz Johnson 142-0701-851 Components Tyco ...
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... AD9212 Qty per Reference Item Board Designator 37 8 R161, R162, R163, R164, R208, R225, R241, R259 38 3 R303, R305, R306 39 1 R414 40 1 R404 41 1 R309 42 5 R310, R501, R535, R601, R634 43 1 R308 44 4 R502, R536, R602, R635 45 16 R513, R514, R518, ...
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... IC SOT-223 ADP3339AKC-1.8-RL, 1.5 A, 1.8 V LDO regulator IC CP-64-3 AD8334ACPZ-REEL, ultralow noise precision dual VGA IC SOT-223 ADP3339AKC-5-RL7 IC SOT-223 ADP3339AKC-3.3-RL IC CP-64-3 AD9212BCPZ-65, octal, 10-bit, 65 MSPS serial LVDS 1.8 V ADC IC SOT-23 ADR510ARTZ, 1.0 V, precision low noise shunt voltage reference IC LFCSP AD9515BCPZ, 1.6 GHz CP-32-2 clock distribution IC IC SC70, NC7WZ07P6X_NL, MAA06A UHS dual buffer ...
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... Notes Range AD9212ABCPZ-40 −40°C to +85°C AD9212ABCPZRL7-40 −40°C to +85°C AD9212ABCPZ-65 −40°C to +85°C AD9212ABCPZRL7-65 −40°C to +85°C 2 AD9212-65EBZ RoHS Compliant Part. 2 Interposer board (HSC-ADC-FIFO5-INTZ) is required to connect to HSC-ADC-EVALCZ data capture board. ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...