AD9212 Analog Devices, AD9212 Datasheet - Page 24

• Manufacturer Part Number: AD9212
• Description: Octal, 10-Bit, 40 MSPS/65 MSPS, Serial LVDS, 1.8 V ADC
• Manufacturer: Analog Devices

Specifications of AD9212

• Resolution (bits): 10bit
• # Chan: 8
• Sample Rate: 65MSPS
• Interface: LVDS,Ser
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9212
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(f
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 56).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9212.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
Refer to the
Application Note
performance as it relates to ADCs.
A
) due only to aperture jitter (t
SNR Degradation = 20 × log 10(1/2 × π × f
130
120
100
110
90
80
70
60
50
40
30
1
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
Figure 56. Ideal SNR vs. Input Frequency and Jitter
AN-501 Application Note
for more in-depth information about jitter
ANALOG INPUT FREQUENCY (MHz)
10
0.125ps
0.25ps
J
0.5ps
1.0ps
2.0ps
) can be calculated by
and the
100
AN-756
A
× t
14 BITS
12 BITS
16 BITS
J
)
1000
Rev. E | Page 24 of 56
Power Dissipation and Power-Down Mode
As shown in Figure 57 and Figure 58, the power dissipated by
the AD9212 is proportional to its sample rate. The digital power
dissipation does not vary much because it is determined primarily
by the DRVDD supply and bias current of the LVDS output drivers.
0.30
0.25
0.20
0.15
0.10
0.05
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
Figure 57. Supply Current vs. f
Figure 58. Supply Current vs. f
0
0
10
10
15
AVDD CURRENT
TOTAL POWER
DRVDD CURRENT
20
20
AVDD CURRENT
TOTAL POWER
DRVDD CURRENT
30
ENCODE (MHz)
ENCODE (MHz)
SAMPLE
SAMPLE
25
40
for f
for f
IN
30
IN
= 10.3 MHz, AD9212-40
= 10.3 MHz, AD9212-65
50
35
Data Sheet
60
40
0.60
0.58
0.56
0.54
0.52
0.50
0.48
0.46
0.44
0.42
0.40
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50