AD9212 Analog Devices, AD9212 Datasheet - Page 6

• Manufacturer Part Number: AD9212
• Description: Octal, 10-Bit, 40 MSPS/65 MSPS, Serial LVDS, 1.8 V ADC
• Manufacturer: Analog Devices

Specifications of AD9212

• Resolution (bits): 10bit
• # Chan: 8
• Sample Rate: 65MSPS
• Interface: LVDS,Ser
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9212
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
Parameter
CLOCK INPUTS (CLK+, CLK−)
LOGIC INPUTS (PDWN, SCLK/DTP)
LOGIC INPUT (CSB)
LOGIC INPUT (SDIO/ODM)
LOGIC OUTPUT (SDIO/ODM)
DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)
DIGITAL OUTPUTS (D + x, D − x),
1
2
3
See the
This is specified for LVDS and LVPECL only.
This is specified for 13 SDIO pins sharing the same connection.
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage (I
Logic 0 Voltage (I
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
Output Coding (Default)
(LOW POWER, REDUCED SIGNAL OPTION)
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
Output Coding (Default)
AN-835 Application
1
OH
OL
= 50 μA)
= 800 μA)
Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
OS
OS
2
3
)
)
OD
OD
)
)
Temperature
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Rev. E | Page 6 of 56
Min
247
1.125
150
1.10
250
1.2
0
1.2
0
1.2
0
1.79
CMOS/LVDS/LVPECL
Typ
1.2
20
1.5
30
0.5
70
0.5
30
2
LVDS
Offset binary
LVDS
Offset binary
AD9212-40
Max
3.6
0.3
3.6
0.3
DRVDD + 0.3
0.3
0.05
454
1.375
250
1.30
Min
1.2
1.2
1.2
247
150
250
0
1.79
1.125
1.10
CMOS/LVDS/LVPECL
Typ
1.2
20
1.5
30
0.5
70
0.5
30
2
LVDS
LVDS
Offset binary
Offset binary
AD9212-65
Max
3.6
0.3
3.6
0.3
DRVDD + 0.3
0.3
0.05
454
1.375
250
1.30
Data Sheet
Unit
mV p-p
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
mV
V
mV
V