AD7457 Analog Devices, AD7457 Datasheet - Page 11

• Manufacturer Part Number: AD7457
• Description: Pseudo Differential Input, 100 kSPS, 12-Bit ADC in 8-Lead SOT-23
• Manufacturer: Analog Devices

Specifications of AD7457

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 100kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: SOT

THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7457 is a 12-bit, low power, single supply, successive
approximation analog-to-digital converter (ADC) with a
pseudo differential analog input. It operates with a single 2.7 V
to 5.25 V power supply and is capable of throughput rates up to
100 kSPS. It requires an external reference to be applied to the
V
The AD7457 has an on-chip differential track-and-hold
amplifier, a successive approximation (SAR) ADC, and a serial
interface housed in an 8-lead SOT-23 package. The serial clock
input accesses data from the part and provides the clock source
for the successive approximation ADC. The AD7457 automati-
cally powers down after conversion, resulting in low power
consumption.
CONVERTER OPERATION
The AD7457 is a successive approximation ADC based around
two capacitive DACs. Figure 14 and Figure 15 show simplified
schematics of the ADC in the acquisition phase and the conver-
sion phase, respectively. The ADC is comprised of control logic,
a SAR, and two capacitive DACs. In Figure 14 (acquisition
phase), SW3 is closed, SW1 and SW2 are in Position A, the
comparator is held in a balanced condition, and the sampling
capacitor arrays acquire the differential signal on the input.
When the ADC starts a conversion (Figure 15), SW3 opens, and
SW1 and SW2 move to Position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribu-
tion DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced, the conversion is complete. The control logic generates
the ADC’s output code. The output impedances of the sources
driving the V
the two inputs have different settling times, resulting in errors.
REF
V
V
IN+
IN –
pin.
B
B
A
A
V
IN+
REF
SW1
SW2
and the V
Figure 14. ADC Acquisition Phase
C
C
S
S
IN–
pins must be matched; otherwise
SW3
COMPARATOR
CAPACITIVE
CAPACITIVE
CONTROL
DAC
LOGIC
DAC
Rev. A | Page 11 of 20
ADC TRANSFER FUNCTION
The output coding for the AD7457 is straight (natural) binary.
The designed code transitions occur at successive LSB values
(1 LSB, 2 LSB, and so on). The LSB size is V
transfer characteristics of the AD7457 are shown in Figure 16.
TYPICAL CONNECTION DIAGRAM
Figure 17 shows a typical connection diagram for the AD7457.
In this setup, the GND pin is connected to the analog ground
plane of the system. The V
a 2.5 V decoupled reference source. The signal source is
connected to the V
dc voltage is connected to the V
ground for the V
AGND with a 10 µF tantalum capacitor in parallel with a 0.1 µF
ceramic capacitor. The reference pin should be decoupled to
AGND with a capacitor of at least 0.33 µF. The conversion result
is output in a 16-bit word with four leading zeros followed by
the MSB of the 12-bit result.
V
V
IN+
IN –
B
B
A
A
111...11
111...10
011...11
111...00
000...10
000...01
000...00
V
REF
Figure 16. Ideal Transfer Characteristics
SW1
SW2
IN+
Figure 15. ADC Conversion Phase
IN+
0V
C
C
input. The V
S
S
1LSB = V
1LSB
analog input via a unity gain buffer. A
REF
REF
pin is connected to the AD780,
SW3
ANALOG INPUT
/4096
IN–
DD
COMPARATOR
pin to provide a pseudo
pin should be decoupled to
V
REF –
REF
/4096. The ideal
1LSB
CAPACITIVE
CAPACITIVE
CONTROL
LOGIC
DAC
DAC
AD7457