AD7457 Analog Devices, AD7457 Datasheet - Page 14

• Manufacturer Part Number: AD7457
• Description: Pseudo Differential Input, 100 kSPS, 12-Bit ADC in 8-Lead SOT-23
• Manufacturer: Analog Devices

Specifications of AD7457

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 100kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: SOT

AD7457
In applications with a slow SCLK, it is possible to read in data
on each SCLK rising edge. In this case, the first falling edge of
SCLK after the CS rising edge clocks out the second leading
zero and can be read in on the following rising edge. If the first
SCLK edge after the CS rising edge is a falling edge, the first
leading zero that was clocked out when CS went high is missed,
unless it was not read on the first SCLK falling edge. The fif-
teenth falling edge of SCLK clocks out the last bit of data, which
can be read in by the following rising SCLK edge.
POWER CONSUMPTION
The AD7457 automatically enters power-down at the end of
each conversion. When in the power-down mode, all analog
circuitry is powered down and the current consumption is 1 µA.
To achieve the specified power consumption (which is the
lowest), there are a few things the user should keep in mind.
The conversion time of the device is determined by the serial
clock frequency. The faster the SCLK frequency, the shorter the
conversion time. Therefore, as the clock frequency used is
increased, the ADC is dissipating power for a shorter period of
time (during conversion) and it remains in power-down for a
longer percentage of the cycle time or throughput rate. This
can be seen in Figure 23, which shows typical I
frequency for V
the maximum throughput of 100 kSPS.
Figure 24 shows typical power consumption vs. throughput rate
for the maximum SCLK frequency of 10 MHz. In this case, the
conversion time is the same for all throughputs, because the
SCLK frequency is fixed. As the throughput rate decreases, the
average power consumption decreases, because the ADC spends
more time in power-down.
2.5
2.0
1.5
1.0
0.5
0
0
V
Figure 23. I
DD
= 3V
DD
2
of 3 V and 5 V, when operating the device at
DD
when Operating at 100 kSPS
vs. SCLK Frequency for V
SCLK Frequency (MHz)
4
V
DD
= 5V
6
DD
= 3 V and 5 V
DD
8
vs. SCLK
T
A
= 25°C
10
Rev. A | Page 14 of 20
MICROPROCESSOR INTERFACING
The serial interface of the AD7457 allows the part to be con-
nected to a range of different microprocessors. This section
explains how to interface the AD7457 with the ADSP-218x
serial interface.
AD7457 to ADSP-218x
The ADSP-218x family of DSPs can be interfaced directly to the
AD7457 without any glue logic. The serial clock for the ADC is
provided by the DSP. SDATA from the ADC is connected to the
data receive (DR) input of the serial port and CS can be con-
trolled by a flag (FL0). The connection diagram is shown in
Figure 25.
SPORT0 must be enabled to receive the conversion data and to
provide the SCLK, while SPORT1 must be configured for flags
and so on.
Figure 24. Power vs. Throughput Rate for SCLK = 10 MHz for V
1
ADDITIONAL PINS OMITTED FOR CLARITY.
2.5
2.0
1.5
1.0
0.5
0
AD7457
0
1
SDATA
SCLK
20
Figure 25. AD7457 to ADSP-218x
CS
THROUGHPUT (kSPS)
V
DD
40
= 5V
60
ADSP-21xx
SCLK
DR0
RFS
FL0
V
DD
= 3V
80
SPORT0
SPORT1
T
1
A
DD
= 25 ° C
= 3 V and 5 V
100