AD7457 Analog Devices, AD7457 Datasheet - Page 5

• Manufacturer Part Number: AD7457
• Description: Pseudo Differential Input, 100 kSPS, 12-Bit ADC in 8-Lead SOT-23
• Manufacturer: Analog Devices

Specifications of AD7457

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 100kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: SOT

TIMING SPECIFICATIONS
V
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
SCLK
CONVERT
2
3
4
5
6
7
8
POWER-UP
POWER-DOWN
The timing specifications are guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
1.6 V. See
Mark/space ratio for the SCLK input is 40/60 to 60/40.
Measured with the load circuit of
cross 0.4 V or 2.0 V for V
t
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
See the
3
3
4
8
DD
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of
2
= 2.7 V to 5.25 V, f
5
Power Consumption
Figure 2
and the Serial
Limit at T
10
10
16 × t
1.6
10
20
40
0.4 t
0.4 t
10
10
35
1
7.4
SDATA
DD
SCLK
SCLK
SCLK
= 3 V.
SCLK
CS
SCLK
section.
= 10 MHz, f
MIN
Interface
Figure 3
POWER
THREE-STATE
UP
, T
MAX
T
T
ACQUISITION
POWERUP
and defined as the time required for the output to cross 0.8 V or 2.4 V with V
section.
TRACK
S
1
= 100 kSPS, V
t
2
CONVERT
START
Unit
kHz min
MHz max
µs max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs max
µs min
4 LEADING ZEROS
0
Figure 2. AD7457 Serial Interface Timing Diagram
t
5
0
t
3
REF
0
t
4
= 2.5 V, T
0
Rev. A | Page 5 of 20
Description
t
CS rising edge to SCLK falling edge setup time
Delay from CS rising edge until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK high pulse width
SCLK low pulse width
SCLK edge to data valid hold time
SCLK falling edge to SDATA three-state enabled
SCLK falling edge to SDATA three-state enabled
Power-up time from full power-down
Minimum time spent in power-down
DB11 DB10
SCLK
t
6
= 1/f
A
= T
SCLK
MIN
HOLD
t
7
to T
DB2
MAX
DB1
t
POWER DOWN
8
, unless otherwise noted.
AUTOMATIC
8
DB0
, quoted in the timing characteristics is the true bus relinquish
T
THREE-STATE
POWERDOWN
Figure 3.
DD
= 5 V, and the time required for the output to
The measured number is then extrapolated
T
T
DD
ACQUISTION
POWERUP
TRACK
) and timed from a voltage level of
AD7457