AD7730L Analog Devices, AD7730L Datasheet - Page 19

• Manufacturer Part Number: AD7730L
• Description: CMOS, 24-Bit Low Power Sigma-Delta ADC for Bridge Transducer Applications
• Manufacturer: Analog Devices

Specifications of AD7730L

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 5MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: (2Vref/PGA Gain) p-p,(Vref/PGA Gain) p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: SOIC,SOP

REV. A
Bit
Location
FR11–FR10
FR9
FR8
FR7–FR6
FR5
FR4
FR3–FR0
CHOP
0
1
0
1
Bit
Mnemonic
ZERO
SKIP
FAST
ZERO
AC
CHP
DL3–DL0
SKIP
0
0
1
1
Description
A zero must be written to these bits to ensure correct operation of the AD7730.
FIR Filter Skip Bit. With a 0 in this bit, the AD7730 performs two stages of filtering before
shipping a result out of the filter. The first is a sinc
1 in this bit, the FIR filter on the part is bypassed and the output of the sinc
as the output result of the AD7730’s filter (see Filter Architecture for more details on the filter
implementation).
FASTStep Mode Enable Bit. A 1 in this bit enables the FASTStep mode on the AD7730. In
this mode, if a step change on the input is detected, the FIR calculation portion of the filter is
suspended and replaced by a simple moving average on the output of the sinc
two outputs from the sinc
outputs used to calculate the moving average output is increased (from 2 to 4 to 8 to 16) until
the STDY bit goes low. When the FIR filter has fully settled after a step, the STDY bit will
become active and the FIR filter is switched back into the processing loop (see Filter Architec-
ture section for more details on the FASTStep mode).
A zero must be written to these bits to ensure correct operation of the AD7730.
AC Excitation Bit. If the signal source to the AD7730 is ac-excited, a 1 must be placed in this
bit. For dc-excited inputs, this bit must be 0. The ac bit has no effect if CHP is 0. With the ac
bit at 1, the AD7730 assumes that the voltage at the AIN(+)/AIN(–) and REF IN(+)/REF IN(–)
input terminals are reversed on alternate input sampling cycles (i.e. chopped). Note that when
the AD7730 is performing internal zero-scale or full-scale calibrations, the ac bit is treated as a
0, i.e., the device performs these self-calibrations with dc excitation.
Chop Enable Bit. This bit determines if the chopping mode on the part is enabled. A 1 in this
bit location enables chopping on the part. When the chop mode is enabled, the part is effectively
chopped at its input and output to remove all offset and offset drift errors on the part. If offset
performance with time and temperature are important parameters in the design, it is recom-
mended that the user enable chopping on the part. If the input signal is dc-excited, the user has
the option of operating the part in either chop or nonchop mode. If the input signal is ac-excited,
both the ac bit and the CHP bit must be set to 1. The chop rate on the ACX and ACX signals is
one half of the programmed output rate of the part and thus the chopping frequency varies with
the programmed output rate.
Delay Selection Bits. These four bits program the delay (in modulator cycles) to be inserted after
each chop edge when the CHP bit is 1. One modulator cycle is MCLK IN/16 and is 3.25 s at
MCLK IN = 4.9152 MHz. A delay should only be required when in ac mode. Its purpose is to
cater for external delays between the switching signals (ACX and ACX) and when the analog
inputs are actually switched and settled. During the specified number of cycles (between 0 and
15), the modulator is held in reset and the filter does not accept any inputs. If CHP = 1, the
output rate is (MCLK IN/ 16 (DL + 3
The chop rate is always one half of the output rate. This chop period takes into account the
programmed delay and the fact that the sinc
the output rate is 1/SF.
SF Range
2048 to 150
2048 to 75
2048 to 40
2048 to 20
Table XV. SF Ranges
3
–19–
filter are used to calculate an AD7730 output. The number of sinc
Output Update Rate Range (Assuming 4.9152 MHz Clock)
150 Hz to 2.048 kHz
50 Hz to 1.365 kHz
150 Hz to 7.6 kHz
50 Hz to 5.12 kHz
SF) where DL is the value loaded to bits DL0–DL3.
3
filter must settle every chop cycle. With CHP = 0,
3
filter followed by a 22-tap FIR filter. With a
AD7730/AD7730L
3
filter. Initially,
3
is fed directly
3