AD7851 Analog Devices, AD7851 Datasheet

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... High Speed Modems Automotive GENERAL DESCRIPTION The AD7851 is a high speed, 14-bit ADC that operates from a single 5 V power supply. The ADC powers up with a set of default conditions at which time it can be operated as a read-only ADC. The ADC contains self-calibration and system calibration options to ensure accurate operation over time and temperature and has a number of power-down options for low power applications ...

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... Mode 1 (2-Wire 8051 Interface Mode 2 (3-Wire SPI/QSPI Interface Mode Mode 3 (QSPI Interface Mode Mode 4 and 5 (Self-Clocking Modes CONFIGURING THE AD7851 . . . . . . . . . . . . . . . . . . . . . 28 AD7851 as a Read-Only ADC . . . . . . . . . . . . . . . . . . . . . 28 Writing to the AD7851 . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Interface Modes 2 and 3 Configuration . . . . . . . . . . . . . . 29 Interface Mode 1 Configuration . . . . . . . . . . . . . . . . . . . . 30 Interface Modes 4 and 5 Configuration . . . . . . . . . . . . . . 30 MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . 31 AD7851 to 8XC51/PIC17C42 Interface . . . . . . . . . . . . . . . 31 AD7851 to 68HC11/16/L11/PIC16C42 Interface ...

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... Straight (Natural) Binary Twos Complement µs max 2.78 3.25 µs max 3.0 3.5 –3– AD7851 = 285 kHz; A and K Grade MHz SAMPLE CLKIN = MIN MAX Test Conditions/Comments Typically SNR Is 79.5 dB kHz, Sine Wave 333 kHz. ...

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... The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7851 can calibrate. Note also that these are voltage spans and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.05 × V allowable system full-scale voltage applied between AIN(+) and AIN(– ...

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... Internal DAC Plus System Full-Scale Calibration Time, Master Clock Dependent (222228 t ms typ System Offset Calibration Time, Master Clock Dependent (27798 t ) CLKIN ns max Delay from CLK to SCLK –5– AD7851 = unless otherwise noted.) A MIN MAX CLKIN ) CLKIN ) and timed from a voltage level of 1.6 V. See ...

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... AD7851 TYPICAL TIMING DIAGRAMS Figures 2 and 3 show typical read and write timing diagrams. Figure 2 shows the reading and writing after conversion in Interface Modes 2 and 3. To attain the maximum sample rate of 285 kHz in Interface Modes 2 and 3, reading and writing must be performed during conversion. Figure 3 shows the timing dia- gram for Interface Modes 4 and 5 with sample rate of 285 kHz ...

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... This board is a complete unit allowing control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators. To order a complete evaluation kit, the particular ADC evaluation board needs to be ordered, e.g., EVAL-AD7851CB, the EVAL-CONTROL BRD2, and trans- former. See the Evaluation Board application note for more information. ...

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... The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02 N +1.76) dB Thus, for a 14-bit converter, this is 86 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7851 defined ...

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... When this input is not used, it should be tied to DV Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL and 2 BUSY remains high until conversion is completed. BUSY is also used to indicate when the AD7851 has completed its on-chip calibration sequence. SLEEP 3 Sleep Input/Low Power Mode ...

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... AD7851 ON-CHIP REGISTERS The AD7851 powers up with a set of default conditions, and the user need not ever write to the device. In this case, the AD7851 will operate as a read-only ADC. The AD7851 still retains the flexibility for performing a full power-down and a full self-calibration. ...

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... Here the system gain error is calibrated out followed by the system offset error. This calibrates out the system offset error only. This calibrates out the system gain error only. –11– AD7851 PMGT0 RDSLT1 CALSLT0 STCAL ...

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... AD7851 STATUS REGISTER The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits in the status register is described below. The power-up status of all bits is 0. ...

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... CALIBRATION REGISTERS The AD7851 has 10 calibration registers in all, 8 for the DAC, 1 for the offset, and 1 for gain. Data can be written to or read from all 10 calibration registers. In self- and system calibration, the part automatically modifies the calibration registers; only if the user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers ...

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... AD7851 START WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1, RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11 CAL REGISTER POINTER IS AUTOMATICALLY RESET READ CAL REGISTER CAL REGISTER POINTER IS AUTOMATICALLY INCREMENTED LAST REGISTER WRITE OPERATION OR ABORT ? YES FINISHED Figure 9. Flowchart for Reading from the Calibration Registers ...

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... V . The reference input to DD the part is buffered on-chip. A major advantage of the AD7851 is that a conversion can be initiated in software as well as applying a signal to the CONVST pin. Another innovative feature of the AD7851 is self-calibration on power-up, which is initiated having a capacitor from the CAL pin to AGND, to give superior dc accuracy (see the Automatic Calibration on Power-On section) ...

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... In a single-supply application (5 V), the V+ and V– of the op amp COMPARATOR HOLD can be taken directly from the supplies to the AD7851 which elimi- nates the need for extra external power supplies. When operating with rail-to-rail inputs and outputs at frequencies greater than 10 kHz, care must be taken in selecting the particular op amp for the application. In particular, for single-supply applications the input amplifiers should be connected in a gain of – ...

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... Output code format is twos complement. REF REF Note that the AIN(–) pin on the AD7851 can be biased up above AGND in the unipolar mode also, if required. The advantage of biasing the lower end of the analog input range away from AGND is that the user does not have to have the analog input swing all the way down to AGND ...

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... F 5V 0.01 F 470nF 10 0.01 F 0.1 F Figure 19. Relevant Connections When Using AV as the Reference AD7851 PERFORMANCE CURVES Figure 20 shows a typical FFT plot for the AD7851 at 333 kHz sample rate and 10 kHz input frequency. 0 /REF pin should IN OUT –20 –40 pin and a 100 nF OUT – ...

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... If the user wishes to power down between conversions at lower throughput rates (that is, <100 kSPS for the AD7851) to achieve better power performances, then the SLEEP pin should be tied logic low. ...

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... When using this mode of operation, the AD7851 is only powered up for the duration of the conver- sion. If the power-up time of the AD7851 is taken µs and it is assumed that the current during power typ, then power consumption as a function of throughput can easily be calculated. The AD7851 has a conversion time of 3.25 µ ...

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... STCAL bit to 1. The timing diagrams that follow involve using the CAL pin. The duration of each of the different types of calibrations is given in Table VIII for the AD7851 with a 6 MHz/7 MHz mas- ter clock. These calibration times are master-clock dependent. REV. B Table VIII ...

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... Figure 27. System Calibration Description System calibration allows the user to take out system errors external to the AD7851 as well as calibrate the errors of the AD7851 itself. The maximum calibration range for the system offset errors is ± and for the system gain errors is REF ± ...

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... System Gain and Offset Interaction The inherent architecture of the AD7851 leads to an interaction between the system offset and gain errors when a system calibra- tion is performed. Therefore recommended to perform the cycle of a system offset calibration followed by a system gain cali- bration twice. Separate system offset and system gain calibrations reduce the offset and gain errors to at least the 14-bit level ...

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... DSP machines that the AD7851 will interface to directly are mentioned here. This does not cover all µCs, µPs, and DSPs. The interface mode of the AD7851 that is mentioned here for a specific µC, µP, or DSP is only a guide and in most cases another interface mode may work just as well. ...

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... DIN BECOMES AN OUTPUT MAX 30ns MIN MIN MAX 50ns MAX DB0 DATA WRITE –25– AD7851 MIN/MAX (CONTINUOUS SCLK), SCLK DB15 DB0 DATA READ DIN BECOMES AN INPUT ...

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... AD7851 Mode 2 (3-Wire SPI/QSPI Interface Mode) Default Interface Mode Figure 35 shows the timing diagram for Interface Mode 2 which is the SPI/QSPI interface mode. Here the SYNC input is active low and may be pulsed or tied permanently low. If SYNC is permanently low, 16 clock pulses must be applied to the SCLK ...

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... SCLK will clock out the CLKIN data on the DOUT pin during conversion. The data on the DIN pin is also clocked in to the AD7851 by the same SCLK for the next conversion. The read/write operations must be complete after 16 clock cycles (which takes 3.25 µs approximately from the rising edge of CONVST assuming a 6 MHz CLKIN) ...

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... In the majority of applications, it will not be necessary to access all of these registers. Figure 40 outlines the sequence used to configure the AD7851 as a read-only ADC. In this case, there is no writing to the on-chip registers and only the conversion result data is read from the part. Interface Mode 1 cannot be used in this case necessary to write to the con- trol register to set Interface Mode 1 ...

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... To enable Serial Interface Mode 1, the user must also write to the part. Figures 41, 42, and 43 shows how to configure the AD7851 for each of the different serial interface modes. The continuous loops on all diagrams indicate the sequence for more than one conversion. The options of using a hardware (pulsing ...

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... Figure 42. Flowchart for Setting Up, Reading, and Writing in Interface Mode 1 Interface Modes 4 and 5 Configuration Figure 43 shows the flowchart for configuring the AD7851 in Interface Modes 4 and 5, the self-clocking modes. In this case not recommended to use the software conversion start option. The read and write operations always occur simultaneously and during conversion ...

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... For the 8XC51, 12 MHz version, the serial clock will run at a maximum of 1 MHz so that the serial interface to the AD7851 will only be running at 1 MHz. The CLKIN signal must be pro- vided separately to the AD7851 from a port line on the 8XC51 or from a source other than the 8XC51 ...

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... FSL0 = 1). A gated clock can be used (GCK = the SCLK tied to the CLKIN of the AD7851, then there must be a con- tinuous clock (GCK = 0). Again the data access and hold times of the DSP5600x and the AD7851 should allow for an SCLK of 7 MHz/6 MHz ...

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... The analog ground plane should be allowed to run under the AD7851 to avoid noise coupling. The power supply lines to the AD7851 should use as large a trace as pos- sible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like ...

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... AD7851 0.180 (4.57) MAX 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN OUTLINE DIMENSIONS 24-Lead Plastic Dual In-Line Package [PDIP] (N-24) Dimensions shown in inches and (millimeters) 1 ...

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... MIN REV. B 24-Lead Shrink Small Outline Package [SSOP] (RS-24) Dimensions shown in millimeters 8.50 8.20 7. 8.20 5.60 7.80 5.30 7.40 5. 1.85 1.75 0.10 2.00 MAX 1.65 COPLANARITY 0.25 0.65 0.38 BSC 0.09 0.22 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-150AG –35– AD7851 0.95 8 0.75 4 0.55 0 ...

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... Updated Figure Updated Figure 18 and Figure Updated Figure Updated Automatic Calibration on Power-On section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Updated Mode 4 and 5 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Updated AD7851 as a Read-Only ADC section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Updated Figure Updated Figure Updated Figures 42 and Updated Figure –36– ...