AD7851 Analog Devices, AD7851 Datasheet - Page 23

• Manufacturer Part Number: AD7851
• Description: 14-Bit, 333 kSPS, Serial Sampling A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7851

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 333kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

System Gain and Offset Interaction
The inherent architecture of the AD7851 leads to an interaction
between the system offset and gain errors when a system calibra-
tion is performed. Therefore, it is recommended to perform the
cycle of a system offset calibration followed by a system gain cali-
bration twice. Separate system offset and system gain calibrations
reduce the offset and gain errors to at least the 14-bit level. By
performing a system offset calibration first and a system gain
calibration second, priority is given to reducing the gain error to
zero before reducing the offset error to zero. If the system errors
are small, a system offset calibration would be performed, fol-
lowed by a system gain calibration. If the systems errors are
large (close to the specified limits of the calibration range), this
cycle would be repeated twice to ensure that the offset and gain
errors were reduced to at least the 14-bit level. The advantage of
doing separate system offset and system gain calibrations is that
the user has more control over when the analog inputs need to
be at the required levels, and the CONVST signal does not have
to be used.
Alternatively, a system (gain + offset) calibration can be per-
formed. It is recommended to perform three system (gain +
offset) calibrations to reduce the offset and gain errors to the
14-bit level. For the system (gain + offset) calibration priority
is given to reducing the offset error to 0 before reducing the
gain error to 0. Thus, if the system errors are small then two
system (gain + offset) calibrations will be sufficient. If the
system errors are large (close to the specified limits of the
calibration range), three system (gain + offset) calibrations
may be required to reduce the offset and gain errors to at
least the 14-bit level. There will never be any need to perform
more than three system (offset + gain) calibrations.
In bipolar mode, the midscale error is adjusted for an offset cali-
bration and the positive full-scale error is adjusted for the gain
calibration; in unipolar mode, the zero-scale error is adjusted for
an offset calibration and the positive full-scale error is adjusted
for a gain calibration.
System Calibration Timing
The calibration timing diagram in Figure 31 is for a full system
calibration where the falling edge of CAL initiates an internal
reset before starting a calibration (note that if the part is in power-
down mode the CAL pulse width must take account of the power-up
time). If a full system calibration is performed in the software, it
is easier to perform separate gain and offset calibrations so
that the CONVST bit in the control register does not have to be
programmed in the middle of the system calibration sequence.
The rising edge of CAL starts calibration of the internal DAC
and causes the BUSY line to go high. If the control register is
set for a full system calibration, the CONVST must be used
also. The full-scale system voltage should be applied to the ana-
log input pins from the start of calibration. The BUSY line will
go low once the DAC and system gain calibration are complete.
REV. B
–23–
Next, the system offset voltage is applied to the AIN pin for a
minimum setup time (t
the CONVST and remains until the BUSY signal goes low. The
rising edge of the CONVST starts the system offset calibration
section of the full system calibration and also causes the BUSY
signal to go high. The BUSY signal will go low after a time t
when the calibration sequence is complete.
The timing for a system (gain + offset) calibration is very similar
to that of Figure 31, the only difference being that the time
t
the internal DAC will not be calibrated. The BUSY signal will
signify when the gain calibration is finished and when the part is
ready for the offset calibration.
The timing diagram for a system offset or system gain calibration is
shown in Figure 32. Here again the CAL is pulsed and the rising
edge of the CAL initiates the calibration sequence (or the calibra-
tion can be initiated in software by writing to the control register).
The rising edge of the CAL causes the BUSY line to go high and it
will stay high until the calibration sequence is finished. The analog
input should be set at the correct level for a minimum setup time
(t
correct level until the BUSY signal goes low.
Figure 32. Timing Diagram for System Gain or System
Offset Calibration
CAL1
SETUP
Figure 31. Timing Diagram for Full System Calibration
CONVST (I/P)
BUSY (O/P)
BUSY (O/P)
will be replaced by a shorter time of the order of t
CAL (I/P)
CAL (I/P)
AIN (I/P)
AIN (I/P)
) of 100 ns before the rising edge of CAL and stay at the
t
1
V
t
1
SYSTEM FULL SCALE
t
t
t
1
15
CAL2
t
SETUP
t
SETUP
= 100ns MIN,
15
= 4
t
= 27798
15
V
t
CLKIN
SYSTEM FULL SCALE
) of 100 ns before the rising edge of
t
CAL1
MAX,
t
CLKIN
t
14
t
= 50 MAX,
SETUP
t
t
CAL1
CAL2
= 222228
OR V
SYSTEM OFFSET
t
AD7851
CLKIN
V
t
OFFSET
16
t
CAL2
MAX,
CAL2
CAL2
as