AD7851 Analog Devices, AD7851 Datasheet - Page 4

• Manufacturer Part Number: AD7851
• Description: 14-Bit, 333 kSPS, Serial Sampling A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7851

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 333kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

AD7851
Parameter
POWER PERFORMANCE
SYSTEM CALIBRATION
NOTES
1
2
3
4
5
6
Specifications subject to change without notice.
Temperature ranges as follows: A Version, –40°C to +125°C; K Version, 0°C to 125°C.
Specifications apply after calibration.
SNR calculation includes distortion and noise components.
All digital inputs at DGND except for CONVST, SLEEP, CAL, and SYNC at DV
CLKIN at DGND when external clock off. All digital inputs at DGND except for CONVST, SLEEP, CAL, and SYNC at DV
The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7851 can calibrate. Note also that these are voltage spans and are
Analog inputs at AGND.
not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.05 × V
allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V
explained in more detail in the Calibration section of the data sheet.
AV
I
Normal Mode Power Dissipation
Sleep Mode Power Dissipation
Offset Calibration Span
Gain Calibration Span
DD
Normal Mode
Sleep Mode
With External Clock On
With External Clock Off
DD,
With External Clock On
With External Clock Off
DV
DD
5
4
6
6
Version A
4.75/5.25
17
20
600
10
300
89.25
52.5
+0.05 × V
+1.025 × V
105
REF
1
REF
/–0.05 × V
/–0.975 × V
89.25
Version K
4.75/5.25
17
20
600
10
300
105
52.5
REF
–4–
REF
DD
1
. No load on the digital outputs. Analog inputs at AGND.
Unit
V min/max
mA max
µA typ
µA typ
µA max
µA typ
mW max
µW typ
µW max
V max/min
V max/min
Test Conditions/Comments
AV
12 mA.
Full Power-Down. Power management bits
in control register set as PMGT1 = 1, PMGT0 = 0.
Partial Power-Down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
Typically 1 µA. Full Power-Down. Power
management bits in control register set as
PMGT1 = 1, PMGT0 = 0.
Partial Power-Down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
V
V
V
Allowable Offset Voltage Span for Calibration.
Allowable Full-Scale Voltage Span for Calibratio
DD
DD
DD
DD
= 5.25 V: Typically 63 mW; SLEEP = V
= 5.25 V; SLEEP = 0 V.
= 5.25 V; Typically 5.25 µW; SLEEP = 0 V.
= DV
DD
= 4.75 V to 5.25 V. Typically
DD
. No load on the digital outputs.
REF
± 0.025 × V
REF
REF
). This is
REV. B
, and the
DD
.
n.