AD5781 Analog Devices, AD5781 Datasheet - Page 22

• Manufacturer Part Number: AD5781
• Manufacturer: Analog Devices

Specifications of AD5781

• Resolution (bits): 18bit
• Dac Update Rate: 1MSPS
• Dac Settling Time: 1µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: Unbuffered Vout
• Dac Input Format: Ser,SPI

AD5781
Asynchronous DAC Update
In this mode, LDAC is held high while data is being clocked
into the input shift register. The DAC output is asynchronously
updated by taking LDAC low after SYNC has been taken high.
The update now occurs on the falling edge of LDAC .
Reset Function ( RESET )
The
either by asserting the RESET pin or by utilizing the software
RESET control function (see
used, it should be hardwired to IOV
Table 9. Hardware Control Pins Truth Table
LDAC
X
X
0
0
1
1
0
1
0
1
ON-CHIP REGISTERS
DAC Register
Table 10 outlines how data is written to and read from the DAC register.
Table 10. DAC Register
MSB
DB23
R/W
R/W
1
The following equation describes the ideal transfer function of the DAC:
where:
V
V
D is the 18-bit code programmed to the DAC.
X is don’t care.
X is don’t care.
1
1
REFN
REFP
AD5781
V
is the positive voltage applied at the V
is the negative voltage applied at the V
OUT
CLR
X
X
0
1
0
1
0
1
0
=
1
X
1
X
(
can be reset to its power-on state by two means:
V
REFP
DB22
0
2
−
1
1
RESET
0
1
1
1
1
1
1
1
1
1
18
V
−
REFN
1
)
×
Table 14
D
Function
The
The
The DAC register is loaded with the clearcode register value, and the output is set accordingly.
The output is set according to the DAC register value.
The DAC register is loaded with the clearcode register value, and the output is set accordingly.
The output is set according to the DAC register value.
The output remains at the clear code value.
The output remains set according to the DAC register value.
The output remains at the clear code value.
The DAC register is loaded with the clearcode register value and the output is set accordingly.
The DAC register is loaded with the clearcode register value and the output is set accordingly.
The output remains at the clear code value.
The output is set according to the DAC register value.
+
Register address
DB21
0
V
AD5781
AD5781
REFN
CC
). If the
.
REFPS
REFNS
is in reset mode. The device cannot be programmed.
is returned to its power-on state. All registers are set to their default values.
RESET pin is not
input pin.
input pin.
DB20
1
Rev. C | Page 22 of 28
DB19
Asynchronous Clear Function (CLR)
The CLR pin is an active low clear that allows the output to be
cleared to a user defined value. The 18-bit clear code value is
programmed to the clearcode register (see
necessary to maintain
to complete the operation (see
is returned high, the output remains at the clear value (if LDAC
is high) until a new value is loaded to the DAC register. The
output cannot be updated with a new value while the CLR pin is
low. A clear operation can also be performed by setting the CLR
bit in the software control register (see
DAC register data
18-bits of data
DB2
CLR low for a minimum amount of time
Figure 2
DB1
X
). When the
Table 14
1
Table 13
Data Sheet
).
). It is
CLR signal
DB0
X
1
X
LSB