AD9743 Analog Devices, AD9743 Datasheet - Page 23

• Manufacturer Part Number: AD9743
• Description: Dual 10-Bit 250 MSPS Digital-to-Analog Converters
• Manufacturer: Analog Devices

Specifications of AD9743

• Resolution (bits): 10bit
• Dac Update Rate: 250MSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

In pin mode, all register bits are reset to their default values
with the exception of those that are controlled by the SPI pins.
Note also that the RESET pin should be allowed to float and
must be pulled low. Connect an external 10 kΩ resistor to
DVSS. This avoids unexpected behavior in noisy environments.
DRIVING THE DAC CLOCK INPUT
The DAC clock input requires a low jitter drive signal. It is a
PMOS differential pair powered from the CVDD18 supply.
Each pin can safely swing up to 800 mV p-p at a common-
mode voltage of about 400 mV. Though these levels are not
directly LVDS-compatible, CLKP and CLKN can be driven by
an ac-coupled, dc-offset LVDS signal, as shown in Figure 29.
Using a CMOS or TTL clock is also acceptable for lower sample
rates. It can be routed through an LVDS translator and then
ac-coupled as described previously, or alternatively, it can be
transformer-coupled and clamped, as shown in Figure 30.
If a sine wave signal is available, it can be transformer-coupled
directly to the DAC clock inputs, as shown in Figure 31.
The 400 mV common-mode bias voltage can be derived from
the CVDD18 supply through a simple divider network, as
shown in Figure 32.
TTL OR CMOS
CLK INPUT
LVDS_N_IN
LVDS_P_IN
Figure 30. TTL or CMOS DAC Clock Drive Circuit
SINE WAVE
287Ω
Figure 31. Sine Wave DAC Clock Drive Circuit
1kΩ
Figure 29. LVDS DAC Clock Drive Circuit
INPUT
Figure 32. DAC Clock VCM Circuit
0.1µF
0.1µF
0.1µF
0.1µF
50Ω
50Ω
1nF
50Ω
CLKN
V
V
CLKP
V
CVDD18
CVSS
50Ω
50Ω
CM
CM
CM
= 400mV
= 400mV
= 400mV
V
BAV99ZXCT
HIGH SPEED
DUAL DIODE
CM
CLKN
CLKP
= 400mV
CLKN
CLKP
Rev. 0 | Page 23 of 28
AD9741/AD9743/AD9745/AD9746/AD9747
It is important to use CVDD18 and CVSS for any clock bias
circuit as noise that is coupled onto the clock from another
power supply is multiplied by the DAC input signal and
degrades performance.
FULL-SCALE CURRENT GENERATION
The full-scale currents on DAC1 and DAC2 are functions of
the current drawn through an external resistor connected to
the FSADJ pin (Pin 54). The required value for this resistor is
10 kΩ. An internal amplifier sets the current through the
resistor to force a voltage equal to the band gap voltage of 1.2 V.
This develops a reference current in the resistor of 120 μA.
0.1µF
REFIO (Pin 55) should be bypassed to ground with a 0.1 μF
capacitor. The band gap voltage is present on this pin and can
be buffered for use in external circuitry. The typical output
impedance is near 5 kΩ. If desired, an external reference can
be connected to REFIO to overdrive the internal reference.
Internal current mirrors provide a means for adjusting the
DAC full-scale currents. The gain for DAC1 and DAC2 can be
adjusted independently by writing to the DAC1FSC<9:0> and
DAC2FSC<9:0> register bits. The default value of 0x01F9 for
the DAC gain registers gives an I
The full-scale output current range is 8.6 mA to 31.7 mA for
register values 0x000 to 0x3FF.
I
10kΩ
FS
35
30
25
20
15
10
FSADJ
5
REFIO
=
0
10,000
1.2
V
1.2V BANDGAP
×
Figure 34. I
AD9747
⎛
⎜
⎝
256
Figure 33. Reference Circuitry
72
+
⎛
⎜
⎝
DAC GAIN CODE
16
3
FS
×
vs. DAC Gain Code
DAC1 GAIN
DAC2 GAIN
DAC
CURRENT
512
SCALING
FS
of 20 mA, where I
n
FSC
⎞
⎟
⎠
768
⎞
⎟
⎠
DAC1
DAC2
DAC FULL SCALE
REFERENCE CURRENT
FS
1024
equals