AD5380 Analog Devices, AD5380 Datasheet
AD5380
Specifications of AD5380
Available stocks
Related parts for AD5380
AD5380 Summary of contents
Page 1
... REG6 14 c REG6 INPUT DAC REG7 REG7 14 m REG7 14 c REG7 ×5 LDAC Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 AD5380 REFGND REFOUT/REFIN SIGNAL_GND (×5) 1.25V/2.5V REFERENCE 14 DAC 0 VOUT DAC 1 VOUT1 VOUT2 R VOUT3 R VOUT4 14 ...
Page 2
... C Serial Interface ..................................................................... 28 Parallel Interface......................................................................... 30 Microprocessor Interfacing....................................................... 31 Application Information................................................................ 33 Power Supply Decoupling ......................................................... 33 Typical Configuration Circuit .................................................. 33 AD5380 Monitor Function ....................................................... 34 Toggle Mode Function............................................................... 34 Thermal Monitor Function....................................................... 35 AD5380 in a MEMS Based Optical Switch............................. 35 Optical Attenuators.................................................................... 36 Utilizing the AD5380 FIFO ...................................................... 37 Outline Dimensions ....................................................................... 38 Ordering Guide .......................................................................... 38 Rev Page ...
Page 3
... MON_OUT pin for external monitoring, and an output amplifier boost mode that allows optimization of the amplifier slew rate. The AD5380 contains a double-buffered parallel interface that features pulse width, an SPI-, QSPI-, -MICROWIRE, -DSP ...
Page 4
... MΩ min Typically 100 MΩ ±1 μA max Typically ± min/max DD Enabled via CR10 in the AD5380 control register. CR12 selects the reference voltage. 2.495/2.505 V min/max At ambient,. CR12 = 1, optimized for 2.5 V operation. 1.22/1.28 V min/max CR12 = 0 ±10 ppm/°C max Temperature range: +25° ...
Page 5
... AD5380-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C. 2 Accuracy guaranteed from VOUT AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5380-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5380 control register; operating the AD5380-5 with a 1.25 V reference will lead to degraded accuracy specifications. 1 AD5380-5 Unit Test Conditions/Comments ...
Page 6
... MΩ min Typically 100 MΩ ±1 μA max Typically ± AVDD/2 V min/max Enabled via CR10 in the AD5380 control register. CR12 selects the reference voltage. 1.245/1.255 V min/max At ambient; CR12 = 0; Optimized for 1.25 V operation 2.47/2.53 V min/max CR12 = 1. ±10 ppm/° ...
Page 7
... Accuracy guaranteed from VOUT = AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5380-3 is 1.25 V. Programmable to 2.5 V via CR12 in the AD5380 control register; operating the AD5380-3 with a 2.5 V reference will lead to degraded accuracy specifications and limited input code range CHARACTERISTICS AVDD = 5.5 V ...
Page 8
... AD5380 TIMING CHARACTERISTICS SERIAL INTERFACE DVDD = 2 5.5 V; AVDD = 3.6 V; AGND = DGND = 0 V; all specifications T unless otherwise noted. Table Parameter Limit MIN 4.5 9 ...
Page 9
... DB0 DB23 NOP CONDITION DB23 SELECTED REGISTER DATA CLOCKED OUT DB0 DB23 INPUT WORD FOR DAC N DB23 INPUT WORD FOR DAC N Rev Page AD5380 48 DB0 DB0 DB0 DB0 ...
Page 10
... AD5380 SERIAL INTERFACE DVDD = 2 5.5 V; AVDD = 3.6 V; AGND = DGND = 0 V; all specifications T unless otherwise noted. Table Parameter Limit MIN MAX F 400 SCL 100 300 300 ...
Page 11
... LDAC rising edge to WR rising edge ns min BUSY rising edge to LDAC falling edge ns min LDAC falling edge to DAC output response time μs typ DAC output settling time ns min CLR pulse width low μsmax CLR pulse activation time Rev Page AD5380 MIN MAX ...
Page 12
... AD5380 REG0, REG1, A5...A0 DB13...DB0 BUSY LDAC VOUT1 LDAC VOUT2 VOUT CLR LDAC ACTIVE DURING BUSY. 2 LDAC ACTIVE AFTER BUSY. Figure 7. Parallel Interface Timing Diagram Rev ...
Page 13
... This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maxi- mum rating conditions for extended periods may affect device reliability. Rev Page AD5380 ...
Page 14
... Ground Reference Point for the Internal Reference. REFOUT/REFIN The AD5380 contains a common REFOUT/REFIN pin. When the internal reference is selected, this pin is the reference output. If the application requires an external reference, it can be applied to this pin and the internal reference can be disabled via the control register. The default for this pin is a reference input. ...
Page 15
... Parallel interface mode is selected when SER/PAR is low. CS/(SYNC/AD0) In parallel interface mode, this pin acts as chip select input (level sensitive, active low). When low, the AD5380 is selected. Serial Interface Mode. This is the frame synchronization input signal for the serial clocks before the addressed register is updated ...
Page 16
... AD5380 Mnemonic Function FIFO EN FIFO Enable (Level Sensitive, Active High). When connected to DVDD, the internal FIFO is enabled, allowing the user to write to the device at full speed. FIFO is only available in parallel interface mode. The status of the FIFO EN pin is sampled on power-up, and also following a CLEAR or RESET, to determine if the FIFO is enabled. In either serial or I interface modes, the FIFO EN pin should be tied low ...
Page 17
... Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) in the linear region of the transfer function, expressed in mV. Offset error is measured on the AD5380-5 with Code 32 loaded into the DAC register, and on the AD5380-3 with Code 64. Gain Error Gain Error is specified in the linear region of the output range between VOUT and VOUT = AVDD – ...
Page 18
... Rev Page 2.0 AVDD = DVDD = 3V V REF 1 25°C A 1.0 0 4096 8192 12288 INPUT CODE Figure 12. Typical AD5380-3 INL Plot –5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 –4.5 –3.5 –2.5 –1.5 –0.5 ...
Page 19
... DVDD DGND 25° 0.9 –2 Rev Page AD5380 VOUT AVDD Figure 18. AD5380 Power-Up Transient AVDD = 5.5V REFIN = 2. 25°C A – INL ERROR DISTRIBUTION (LSB) Figure 19. INL Distribution PD AVDD = DVDD = 2.5V REF VOUT T = 25°C A EXITS HARDWARE PD TO MIDSCALE Figure 20 ...
Page 20
... REFOUT = 1.25V 100 0 100 1k 10k FREQUENCY (Hz) Figure 23. REFOUT Noise Spectral Density V = 2.5V REF T = 25°C A – Figure 24. AD5380-3 Output Amplifier Source and Sink Capability 2.456 AVDD = 2.5V REF T = 25°C A 2.455 2.454 2.453 2.452 2.451 2.450 2.449 1.50 1.75 2.00 100k Rev Page ...
Page 21
... V is recom- mended for the AD5380-5, and 1.25 V for the AD5380-3. DATA DECODING The AD5380 contains a 14-bit data bus, DB13 to DB0. Depend- ing on the value of REG1 and REG0 (see Table 3), this data is AVDD loaded into the addressed DAC input registers, offset (c) registers, or gain (m) registers ...
Page 22
... AD5380 ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) The AD5380 contains a number of special function registers (SFRs), as outlined in Table 15. SFRs are addressed with REG1 = REG0 = 0 and are decoded using Address Bits A5 to A0. Table 15. SFR Register Functions (REG1 = 0, REG0 = 0) R ...
Page 23
... AD5380. CR12 is programmed as follows: CR12 = 1: Internal reference is 2.5 V (AD5380-5 default), the recommended operating reference for AD5380-5. CR12 = 0: Internal reference is 1.25 V (AD5380-3 default), the recommended operating reference for AD5380-3. CR11: Current Boost Control. This bit is used to boost the current in the output amplifier, thereby altering its slew rate. ...
Page 24
... AD5380 Table 18. AD5380 Channel Monitor Decoding REG1 REG0 ...
Page 25
... BUSY AND LDAC FUNCTIONS BUSY is a digital CMOS output that indicates the status of the AD5380. The value of x2, the internal data loaded to the DAC data register, is calculated each time the user writes new data to the corresponding x1 registers. During the calculation of x2, the BUSY output goes low ...
Page 26
... A1 A0 Figure 3 and Figure 5 show timing diagrams for a serial write to the AD5380 in standalone and daisy-chain modes. The 24-bit data-word format for the serial interface is shown in Table 19. A /B. When toggle mode is enabled, this pin selects whether the data write is to the register. With toggle disabled, this bit should be set to zero to select the A data register ...
Page 27
... SDO. Figure 30 shows the readback sequence. For example, to read back the m register of Channel 0 on the AD5380, the following sequence should be implemented. First, write 0x404XXX to the AD5380 input register. This configures the AD5380 for read mode with the m register of Channel 0 selected. Note that Data Bits DB13 to DB0 are don’ ...
Page 28
... START condition followed by the 7-bit slave address. When idle, the AD5380 waits for a START condition followed by its slave address. The LSB of the address word is the Read/ Write ( bit. The AD5380 is a receive only device; when 2 C communicating with the AD5380 After receiving the ...
Page 29
... SDA REG1 REG0 MSB MOST SIGNIFICANT DATA BYTE AD1 AD0 R ACK BY MSB AD538x LSB MSB ACK BY AD538x 2 Figure 31. 4-Byte AD5380 Write Operation AD1 AD0 R ACK BY MSB AD538x LSB MSB ACK BY AD538x DATA FOR CHANNEL "N" ACK BY ...
Page 30
... The REG0 and REG1 pins determine the destination register of the data being written to the AD5380. See Table 11. Pins Each of the 40 DAC channels can be individually addressed. Pins DB13 to DB0 The AD5380 accepts a straight 14-bit parallel word on DB13 to DB0, where DB13 is the MSB and DB0 is the LSB. AD1 AD0 R/W ...
Page 31
... The lower address lines from the processor are connected the AD5380. The upper address lines are decoded to provide LDAC signal for the AD5380. The fast interface timing of the AD5380 allows direct interface to a wide variety of microcontrollers and DSPs, as shown in Figure 35. ...
Page 32
... MSB first. Since the 8051 outputs the LSB first, the transmit routine must take this into account. 8XC51 AD5380 to ADSP-2101/ADSP-2103 Figure 38 shows a serial interface between the AD5380 and the AD5380 ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should SER/PAR be set up to operate in SPORT transmit alternate framing mode. ...
Page 33
... The printed circuit board on which the AD5380 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5380 system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only, a star ground point established as close to the device as possible ...
Page 34
... CR6 to CR2 in the control register. See the AD5380 control register description. Figure 42 shows a block diagram of toggle mode implementation. Each of the 40 DAC channels on the AD5380 contain an A and B data register. Note that the B registers can only be loaded when toggle mode is enabled. The sequence of events when configuring the AD5380 for toggle mode is 1 ...
Page 35
... DACs that offer high channel density with 14-bit monotonic behavior. The 40-channel, 14-bit AD5380 DAC satisfies these requirements. In the circuit in Figure 43, the outputs of the AD5380 are amplified to achieve an output range 200 V, which is used to control actuators that determine the position of MEMS mirrors in an optical switch ...
Page 36
... PORTS OPTICAL SWITCH PHOTODIODES 11 ATTENUATOR 12 ATTENUATOR 1n–1 ATTENUATOR 1n ATTENUATOR N:1 MULTIPLEXER AD5380, 40-CHANNEL, 14-BIT DAC CONTROLLER 16-BIT ADC Figure 44. OADM Using the AD5380 as Part of an Optical Attenuator Rev Page DWDM OUT AWG FIBRE TIA/LOG AMP (AD8304/AD8305) ADG731 (40:1 MUX) AD7671 (0V TO 5V, 1MSPS) ...
Page 37
... In such systems, as many as 400 channels need to be updated within 40 μs. Four-hundred channels requires the use of 10 AD5380s. With FIFO mode enabled, the data write cycle time is 40 ns; therefore, each group consisting of 40 channels can be fully loaded in 1.6 μs. In FIFO mode, a complete group of 40 channels will update in 14.4 μ ...
Page 38
... ROTATED 90° CCW ORDERING GUIDE Model Resolution Temperature Range AD5380BST-3 14 Bits –40°C to +85°C AD5380BST-3-REEL 14 Bits –40°C to +85°C AD5380BST-5 14 Bits –40°C to +85°C AD5380BST-5-REEL 14 Bits –40°C to +85°C EVAL-AD5380EB 16.00 BSC SQ 1.60 MAX 14.00 BSC SQ 0.75 100 1 0.60 0.45 PIN 1 TOP VIEW (PINS DOWN) 0 ...
Page 39
... NOTES Rev Page AD5380 ...
Page 40
... AD5380 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...