AD5380 Analog Devices, AD5380 Datasheet - Page 28

• Manufacturer Part Number: AD5380
• Description: 40-Channel 14-Bit 3 V/5 V Single-Supply Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5380

• Resolution (bits): 14bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Par,Ser,SPI

AD5380
I
The AD5380 features an I
consisting of a serial data line (SDA) and a serial clock line
(SCL). SDA and SCL facilitate communication between the
AD5380 and the master at rates up to 400 kHz. Figure 6
shows the 2-wire interface timing diagrams that incorporate
three different modes of operation. In selecting the I
operating mode, first configure serial operating mode
(SER/ PAR = 1) and then select I
SPI /I
as a slave device (that is, no clock is generated by the AD5380).
The AD5380 has a 7-bit slave address 1010 1(AD1)(AD0).
The 5 MSBs are hard-coded, and the 2 LSBs are determined
by the state of the AD1 and AD0 pins. The facility to hardware-
configure AD1 and AD0 allows four of these devices to be
configured on the bus.
I
One data bit is transferred during each SCL clock cycle. The
data on SDA must remain stable during the high period of the
SCL clock pulse. Changes in SDA while SCL is high are control
signals that configure START and STOP conditions. Both SDA
and SCL are pulled high by the external pull-up resistors when
the I
START and STOP Conditions
A master device initiates communication by issuing a START
condition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high. A START condition
from the master signals the beginning of a transmission to
the AD5380. The STOP condition frees the bus. If a repeated
START condition (Sr) is generated instead of a STOP condition,
the bus remains active.
Repeated START Conditions
A repeated START (Sr) condition may indicate a change of data
direction on the bus. Sr may be used when the bus master is
writing to several I
the bus.
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to any
8-bit data-word. ACK is always generated by the receiving
device. The AD5380 devices generate an ACK when receiving
an address or data by pulling SDA low during the ninth clock
period. Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs if a receiv-
ing device is busy or if a system fault has occurred. In the
event of an unsuccessful data transfer, the bus master should
reattempt communication.
2
2
C Data Transfer
C SERIAL INTERFACE
2
2
C bus is not busy.
C pin to a Logic 1. The device is connected to the I
2
C devices and wants to maintain control of
2
C-compatible 2-wire interface
2
C mode by configuring the
2
C
2
C bus
Rev. A | Page 28 of 40
AD5380 Slave Addresses
A bus master initiates communication with a slave device by
issuing a START condition followed by the 7-bit slave address.
When idle, the AD5380 waits for a START condition followed
by its slave address. The LSB of the address word is the Read/
Write (R/ W ) bit. The AD5380 is a receive only device; when
communicating with the AD5380, R/ W = 0. After receiving the
proper address 1010 1(AD1)(AD0), the AD5380 issues an ACK
by pulling SDA low for one clock cycle.
The AD5380 has four different user programmable addresses
determined by the AD1 and AD0 bits.
Write Operation
There are three specific modes in which data can be written to
the AD5380 DAC.
4-Byte Mode
When writing to the AD5380 DACs, the user must begin with
an address byte (R/ W = 0), after which the DAC acknowledges
that it is prepared to receive data by pulling SDA low. The
address byte is followed by the pointer byte; this addresses the
specific channel in the DAC to be addressed and is also
acknowledged by the DAC. Two bytes of data are then written
to the DAC, as shown in Figure 31. A STOP condition follows.
This allows the user to update a single channel within the
AD5380 at any time and requires four bytes of data to be
transferred from the master.
3-Byte Mode
In 3-byte mode, the user can update more than one channel in a
write sequence without having to write the device address byte
each time. The device address byte is only required once; sub-
sequent channel updates require the pointer byte and the data
bytes. In 3-byte mode, the user begins with an address byte
(R/ W = 0), after which the DAC will acknowledge that it is
prepared to receive data by pulling SDA low. The address byte
is followed by the pointer byte. This addresses the specific chan-
nel in the DAC to be addressed and is also acknowledged by the
DAC. This is then followed by the two data bytes. REG1 and
REG0 determine the register to be updated.
If a STOP condition does not follow the data bytes, another
channel can be updated by sending a new pointer byte followed
by the data bytes. This mode only requires three bytes to be
sent addressed, and reduces the software overhead in updating
the AD5380 channels. A STOP condition at any time exits this
mode. Figure 32 shows a typical configuration.