AD5330

Manufacturer Part NumberAD5330
Description
ManufacturerAnalog Devices
AD5330 datasheet
 


Specifications of AD5330

Resolution (bits)8bitDac Update Rate167kSPS
Dac Settling Time6µsMax Pos Supply (v)+5.5V
Single-supplyYesDac TypeVoltage Out
Dac Input FormatPar  
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FEATURES
AD5330: single 8-bit DAC in 20-lead TSSOP
AD5331: single 10-bit DAC in 20-lead TSSOP
AD5340: single 12-bit DAC in 24-lead TSSOP
AD5341: single 12-bit DAC in 20-lead TSSOP
Low power operation: 115 μA @ 3 V, 140 μA @ 5 V
Power-down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin
2.5 V to 5.5 V power supply
Double-buffered input logic
Guaranteed monotonic by design over all codes
Buffered/unbuffered reference input options
Output range: 0 V to V
or 0 V to 2 × V
REF
Power-on reset to 0 V
Simultaneous update of DAC outputs via LDAC pin
Asynchronous CLR facility
Low power parallel data interface
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
BUF
1
GAIN
8
DB
20
7
. .
DB
13
0
6
CS
7
WR
CLR
9
10
LDAC
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
2.5 V to 5.5 V, 115 μA, Parallel Interface
Single Voltage-Output 8-/10-/12-Bit DACs
AD5330/AD5331/AD5340/AD5341
GENERAL DESCRIPTION
The AD5330/AD5331/AD5340/AD5341
bit DACs. They operate from a 2.5 V to 5.5 V supply consuming
just 115 μA at 3 V and feature a power-down mode that further
reduces the current to 80 nA. The devices incorporate an on-chip
output buffer that can drive the output to both supply rails, but
the AD5330, AD5340, and AD5341 allow a choice of buffered
or unbuffered reference input.
The AD5330/AD5331/AD5340/AD5341 have a parallel
interface. CS selects the device and data is loaded into the
input registers on the rising edge of WR .
REF
The GAIN pin allows the output range to be set at 0 V to V
0 V to 2 × V
Input data to the DACs is double-buffered, allowing simultane-
ous update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the input register and the DAC register to all zeros.
These devices also incorporate a power-on reset circuit that
ensures that the DAC output powers on to 0 V and remains
there until valid data is written to the device.
The AD5330/AD5331/AD5340/AD5341 are available in thin
shrink small outline packages (TSSOP).
1
Protected by U.S. Patent Number 5,969,657.
FUNCTIONAL BLOCK DIAGRAM
V
REF
3
POWER-ON
RESET
INPUT
DAC
REGISTER
REGISTER
8-BIT
DAC
RESET
Figure 1. AD5330
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
1
are single 8-/10-/12-
.
REF
V
DD
12
AD5330
BUFFER
4
V
OUT
POWER-DOWN
LOGIC
11
5
PD
GND
www.analog.com
©2000–2008 Analog Devices, Inc. All rights reserved.
or
REF

AD5330 Summary of contents

  • Page 1

    ... V and feature a power-down mode that further reduces the current to 80 nA. The devices incorporate an on-chip output buffer that can drive the output to both supply rails, but the AD5330, AD5340, and AD5341 allow a choice of buffered or unbuffered reference input. The AD5330/AD5331/AD5340/AD5341 have a parallel interface ...

  • Page 2

    ... Power-Down Mode ........................................................................ 19 Suggested Databus Formats .......................................................... 20 Applications Information .............................................................. 21 Typical Application Circuits ..................................................... 21 Driving V From the Reference Voltage ............................... 21 DD Bipolar Operation Using the AD5330/AD5331/ AD5340/AD5341 ......................................................................... 21 Decoding Multiple AD5330/AD5331/ AD5340/AD5341 .... 21 Programmable Current Source ................................................ 22 Power Supply Bypassing and Grounding ................................ 22 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 25 Rev Page ...

  • Page 3

    ... Lower deadband exists only if offset error is negative upper deadband exists only ΔV = ±10% DD Buffered reference (AD5330, AD5340, and AD5341) Unbuffered reference Buffered reference (AD5330, AD5340, and AD5341) Unbuffered reference; gain = 1, input impedance = R Unbuffered reference; gain = 2, input impedance = R Frequency = 10 kHz Rail-to-rail operation ...

  • Page 4

    ... See the Terminology section. 2 Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C. 3 Linearity is tested using a reduced code range: AD5330 (Code 8 to Code 255); AD5331 (Code 28 to Code 1023); AD5340/AD5341 (Code 115 to Code 4095 specifications tested with output unloaded. 5 This corresponds to x codes ...

  • Page 5

    ... Time between WR cycles. ) and timed from a voltage level NOTES: 1 SYNCHRONOUS LDAC UPDATE MODE 2 ASYNCHRONOUS LDAC UPDATE MODE Figure 2. Parallel Interface Timing Diagram Rev Page AD5330/AD5331/AD5340/AD5341 + V )/ ...

  • Page 6

    ... AD5330/AD5331/AD5340/AD5341 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Parameter V to GND DD Digital Input Voltage to GND Digital Output Voltage to GND Reference Input Voltage to GND V to GND OUT Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature TSSOP Package Power Dissipation θ ...

  • Page 7

    ... RESET 9 CLR 10 LDAC Figure 3. AD5330 Functional Block Diagram Table 5. AD5330 Pin Function Descriptions Pin No. Mnemonic Description 1 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered Connect Reference Input. ...

  • Page 8

    ... AD5330/AD5331/AD5340/AD5341 POWER-ON RESET INPUT GAIN 8 REGISTER RESET 9 CLR LDAC 10 Figure 5. AD5331 Functional Block Diagram Table 6. AD5331 Pin Function Descriptions Pin No. Mnemonic Description 1 DB Parallel Data Input Most Significant Bit of Parallel Data Input. ...

  • Page 9

    ... Ten Parallel Data Inputs REF AD5340 DAC REGISTER 12-BIT BUFFER DAC POWER-DOWN LOGIC 13 PD GND Rev Page AD5330/AD5331/AD5340/AD5341 BUF OUT V 4 REF 12-BIT V 5 OUT AD5340 NC 6 TOP VIEW (Not to Scale) ...

  • Page 10

    ... AD5330/AD5331/AD5340/AD5341 POWER-ON RESET HIGH BYTE REGISTER BUF 2 GAIN LOW BYTE REGISTER HBEN RESET 7 WR CLR 9 LDAC 10 Figure 9. AD5341 Functional Block Diagram Table 8. AD5341 Pin Function Descriptions Pin No. Mnemonic Description 1 HBEN High Byte Enable Pin. This pin is used when writing to the device to determine if data is written to the high byte register or the low byte register ...

  • Page 11

    ... OFFSET POSITIVE GAIN ERROR NEGATIVE GAIN ERROR AMPLIFIER FOOTROOM (~1mV) ACTUAL IDEAL NEGATIVE OFFSET Rev Page AD5330/AD5331/AD5340/AD5341 GAIN ERROR AND OFFSET ERROR ACTUAL IDEAL DAC CODE Figure 12. Positive Offset Error and Gain Error GAIN ERROR AND OFFSET ERROR ACTUAL IDEAL ...

  • Page 12

    ... AD5330/AD5331/AD5340/AD5341 Offset Error Drift This is a measure of the change in offset error with changes in temperature expressed in (ppm of full-scale range)/°C. Gain Error Drift This is a measure of the change in gain error with changes in temperature expressed in (ppm of full-scale range)/°C. Power-Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage ...

  • Page 13

    ... TYPICAL PERFORMANCE CHARACTERISTICS 1 25° 0.5 0 –0.5 –1 100 150 CODE Figure 14. AD5330 Typical INL Plot 25° –1 –2 –3 0 200 400 500 CODE Figure 15. AD5331 Typical INL Plot 25° –4 – ...

  • Page 14

    ... Figure 21. AD5330 INL Error and DNL Error vs. Temperature 1 REF 0.5 GAIN ERROR 0 OFFSET ERROR –0.5 –1.0 – TEMPERATURE (°C) Figure 22. AD5330 Offset Error and Gain Error vs. Temperature –0.1 –0.2 –0.3 –0.4 –0.5 –0 REF MIN DNL 80 120 80 120 Rev Page 0 25° ...

  • Page 15

    ... 1000 800 600 400 200 (V) LOGIC Figure 28. Supply Current vs. Logic Input Voltage AD5330/AD5331/AD5340/AD5341 CH2 CLK 5V CH1 1V 5.0 5.5 Figure 29. Half-Scale Settling (¼ to ¾ Scale Code Change REF CH1 2V CH2 200mV 5.0 5 ...

  • Page 16

    ... AD5330/AD5331/AD5340/AD5341 100 110 120 130 140 150 160 170 I (µA) DD Figure 32. I Histogram with and 0.917 0.916 0.915 0.914 0.913 0.912 0.911 0.910 0.909 0.908 0.907 0.906 0.905 0.904 0.903 250ns/DIV Figure 33. AD5340 Major-Code Transition Glitch Energy – ...

  • Page 17

    ... Because string of resistors guaranteed monotonic. DAC REFERENCE INPUT There is a reference input pin for the DAC. The reference input is buffered on the AD5330, AD5340, and AD5341 but can be configured as unbuffered also. The reference input of the AD5331 is unbuffered. The buffered/unbuffered option is controlled by the BUF pin. ...

  • Page 18

    ... LDAC was brought low. Normally, when LDAC is brought low, the DAC register is filled with the contents of the input register. In the case of the AD5330/ AD5331/AD5340/AD5341, the parts only update the DAC register if the input register has been changed since the last time the DAC register was updated ...

  • Page 19

    ... POWER-DOWN MODE The AD5330/AD5331/AD5340/AD5341 have low power consumption, dissipating only 0.35 mW with supply and 0.7 mW with supply. Power consumption can be further reduced when the DAC is not in use by putting it into power- down mode, which is selected by taking Pin PD low. When the PD pin is high, the DAC works normally with a typical power consumption of 140 μ ...

  • Page 20

    ... DAC devices can be controlled using common GAIN and BUF lines. In the case of the AD5330, this means that the databus must be wider than eight bits. The AD5331 and AD5340 databuses must be at least 10 bits and 12 bits wide, respectively, and are best suited to a 16-bit databus system ...

  • Page 21

    ... AD780/REF192 WITH V . Because this AD589 WITH V DD Figure 45. Bipolar Operation using the AD5330/AD5331/AD5340/AD5341 DECODING MULTIPLE AD5330/AD5331/ AD5340/AD5341 The CS pin on these devices can be used in applications to decode a number of DACs. In this application, all DACs in the system receive the same data and WR pulses, but only CS to one ...

  • Page 22

    ... INPUTS point only. The star ground point should be established as CLR CS closely as possible to the device. The AD5330/AD5331/ AD5340/AD5341 should have ample supply bypassing of 10 μF in parallel with 0.1 μF on the supply located as close to the package as possible, ideally right up against the device. The 10 μF capacitors are the tantalum bead type. The 0.1 μF ...

  • Page 23

    ... AD5325 12 4 AD5306 8 4 AD5316 10 4 AD5326 12 4 AD5307 8 4 AD5317 10 4 AD5327 12 4 AD5330/AD5331/AD5340/AD5341 Additional Pin Functions Pins Settling Time BUF GAIN REF 6 μs BUF GAIN 7 μs GAIN 8 μs BUF GAIN 8 μs BUF GAIN 6 μs 7 μs BUF GAIN 8 μs ...

  • Page 24

    ... AD5330/AD5331/AD5340/AD5341 OUTLINE DIMENSIONS COPLANARITY 0.15 0.05 6.60 6.50 6. 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.20 0.05 0.09 0.30 0.19 SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 48. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 7.90 7.80 7. 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.30 0.20 SEATING 0.19 PLANE 0.09 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 49. 24-Lead Thin Shrink Small Outline Package [TSSOP] ...

  • Page 25

    ... AD5330BRU-REEL7 –40°C to +105°C 1 AD5330BRUZ –40°C to +105°C 1 AD5330BRUZ-REEL –40°C to +105°C 1 AD5330BRUZ-REEL7 –40°C to +105°C AD5331BRU –40°C to +105°C AD5331BRU-REEL –40°C to +105°C AD5331BRU-REEL7 –40°C to +105°C 1 AD5331BRUZ –40°C to +105°C ...

  • Page 26

    ... AD5330/AD5331/AD5340/AD5341 NOTES Rev Page ...

  • Page 27

    ... NOTES AD5330/AD5331/AD5340/AD5341 Rev Page ...

  • Page 28

    ... AD5330/AD5331/AD5340/AD5341 NOTES ©2000–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06852-0-2/08(A) Rev Page ...