AD5330 Analog Devices, AD5330 Datasheet - Page 5
AD5330
Manufacturer Part Number
AD5330
Description
Manufacturer
Analog Devices
Datasheet
1.AD5330.pdf
(28 pages)
Specifications of AD5330
Resolution (bits)
8bit
Dac Update Rate
167kSPS
Dac Settling Time
6µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
Par
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TIMING CHARACTERISTICS
V
Table 3.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
1
2
3
4
5
6
7
8
9
10
11
12
13
Guaranteed by design and characterization, not production tested.
All input signals are specified with t
See Figure 2.
DD
= 2.5 V to 5.5 V, all specifications T
Limit at T
0
0
20
5
4.5
5
5
4.5
5
4.5
20
20
50
MIN
R
= t
, T
F
1, 2, 3
= 5 ns (10% to 90% of V
MAX
LDAC
LDAC
DATA,
GAIN,
HBEN
BUF,
CLR
WR
CS
MIN
1
2
NOTES:
1
2
SYNCHRONOUS LDAC UPDATE MODE
ASYNCHRONOUS LDAC UPDATE MODE
to T
MAX
, unless otherwise noted.
t
Figure 2. Parallel Interface Timing Diagram
1
DD
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
) and timed from a voltage level of (V
t
6
t
3
Rev. A | Page 5 of 28
t
t
t
7
9
4
t
2
t
t
Condition/Comments
CS to WR setup time.
CS to WR hold time.
WR pulse width.
Data, GAIN, BUF, HBEN setup time.
Data, GAIN, BUF, HBEN hold time.
Synchronous mode; WR falling to LDAC falling.
Synchronous mode; LDAC falling to WR rising.
Synchronous mode; WR rising to LDAC rising.
Asynchronous mode; LDAC rising to WR rising.
Asynchronous mode; WR rising to LDAC falling.
LDAC pulse width.
CLR pulse width.
Time between WR cycles.
5
8
t
10
t
13
t
11
AD5330/AD5331/AD5340/AD5341
IL
t
12
+ V
IH
)/2.