AD5302 Analog Devices, AD5302 Datasheet - Page 15

• Manufacturer Part Number: AD5302
• Manufacturer: Analog Devices

Specifications of AD5302

• Resolution (bits): 8bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

SERIAL INTERFACE
The AD5302/AD5312/AD5322 are controlled over a versatile,
3-wire serial interface, which operates at clock rates up to 30 MHz
and is compatible with SPI, QSPI, MICROWIRE, and DSP
interface standards.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide (see Figure 30 to Figure 32).
Data is loaded into the device as a 16-bit word under the control
of a serial clock input, SCLK. The timing diagram for this
operation is shown in Figure 2. The 16-bit word consists of four
control bits followed by 8, 10, or 12 bits of DAC data, depending
on the device type. The first bit loaded is the MSB (Bit 15),
which determines whether the data is for DAC A or DAC B.
Bit 14 determines if the reference input is buffered or unbuffered.
Bit 13 and Bit 12 control the operating mode of the DAC.
Table 6. Control Bits
Bit
15
14
13
12
The remaining bits are DAC data bits, starting with the MSB and
ending with the LSB. The AD5322 uses all 12 bits of DAC data,
the AD5312 uses 10 bits and ignores the 2 LSB. The AD5302 uses
eight bits and ignores the last four bits. The data format is straight
binary, with all 0s corresponding to 0 V output, and all 1s
corresponding to full-scale output (VREF – 1 LSB).
The SYNC input is a level-triggered input that acts as a frame
synchronization signal and chip enable. Data can only be
transferred into the device while SYNC is low. To start the serial
data transfer, SYNC should be taken low observing the minimum
SYNC to SCLK active edge setup time, t
serial data is shifted into the device’s input shift register on the
BIT 15
(MSB)
BIT 15
(MSB)
BIT 15
(MSB)
A/B
A/B
A/B
BUF
BUF
BUF
Name
A/B
BUF
PD1
PD0
PD1
PD1
PD1
Figure 30. AD5302 Input Shift Register Contents
Figure 31. AD5312 Input Shift Register Contents
Figure 32. AD5322 Input Shift Register Contents
PD0
PD0
PD0
Function
0: Data Written to DAC A
1: Data Written to DAC B
0: Reference Is Unbuffered
1: Reference Is Buffered
Mode Bit
Mode Bit
D11 D10
D7
D9
D6
D8
D5
D7
D9
DATA BITS
D4
D6
D8
DATA BITS
D3
D5
D7
DATA BITS
D2
D4
D6
4
. After SYNC goes low,
D1
D3
D5
D0
D2
D4
Power-On Default
N/A
0
0
0
D1
D3
X
D0
D2
X
D1
X
X
BIT 0
(LSB)
BIT 0
(LSB)
BIT 0
(LSB)
D0
X
X
Rev. D | Page 15 of 24
falling edges of SCLK for 16 clock pulses. Any data and clock
pulses after the 16
transfers occur until SYNC is taken high and low again.
SYNC can be taken high after the falling edge of the 16
pulse, observing the minimum SCLK falling edge to SYNC
rising edge time, t
After the end of serial data transfer, data is automatically
transferred from the input shift register to the input register of
the selected DAC. If SYNC is taken high before the 16
edge of SCLK, the data transfer is aborted and the input
registers are not updated.
When data has been transferred into both input registers, the
DAC registers of both DACs can be simultaneously updated by
taking LDAC low.
LOW POWER SERIAL INTERFACE
To reduce the power consumption of the device even further,
the interface only powers up fully when the device is being
written to. As soon as the 16-bit control word has been written
to the part, the SCLK and DIN input buffers are powered down.
They only power up again following a falling edge of SYNC .
DOUBLE-BUFFERED INTERFACE
The AD5302/AD5312/AD5322 DACs all have double-buffered
interfaces consisting of two banks of registers—input registers and
DAC registers. The input register is connected directly to the input
shift register and the digital code is transferred to the relevant input
register on completion of a valid write sequence. The DAC
register contains the digital code used by the resistor string.
Access to the DAC register is controlled by the LDAC function.
When LDAC is high, the DAC register is latched and the input
register can change state without affecting the contents of the
DAC register. However, when LDAC is brought low, the DAC
register becomes transparent and the contents of the input
register are transferred to it.
This is useful if the user requires simultaneous updating of both
DAC outputs. The user can write to both input registers
individually and then, by pulsing the LDAC input low, both
outputs update simultaneously.
These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
the last time that LDAC was brought low. Normally, when
LDAC is brought low, the DAC registers are filled with the
contents of the input registers. In the case of the AD5302/
AD5312/AD5322, the part only updates the DAC register if
the input register has been changed since the last time the
DAC register was updated, thereby removing unnecessary
digital crosstalk.
7
th
.
are ignored, and no further serial data
AD5302/AD5312/AD5322
th
th
falling
SCLK