AD5302 Analog Devices, AD5302 Datasheet - Page 19

• Manufacturer Part Number: AD5302
• Manufacturer: Analog Devices

Specifications of AD5302

• Resolution (bits): 8bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

OPTO-ISOLATED INTERFACE FOR PROCESS
CONTROL APPLICATIONS
Each AD5302/AD5312/AD5322 has a versatile 3-wire serial
interface, making them ideal for generating accurate voltages in
process control and industrial applications. Due to noise, safety
requirements, or distance, it can be necessary to isolate the
AD5302/AD5312/AD5322 from the controller. This can easily
be achieved by using opto-isolators, which provide isolation in
excess of 3 kV. The serial loading structure of the AD5302/
AD5312/AD5322 makes them ideally suited for use in opto-
isolated applications. Figure 41 shows an opto-isolated interface
to the AD5302/AD5312/AD5322 where DIN, SCLK, and SYNC
are driven from opto-couplers. The power supply to the part
also needs to be isolated by using a transformer. On the DAC
side of the transformer, a 5 V regulator provides the 5 V supply
required for the AD5302/AD5312/AD5322.
DECODING MULTIPLE AD5302/AD5312/AD5322s
The SYNC pin on the AD5302/AD5312/AD5322 can be used in
applications to decode a number of DACs. In this application,
all the DACs in the system receive the same serial clock and serial
data, but only the SYNC to one of the devices is active at any one
time, allowing access to two channels in this eight-channel system.
POWER
SYNC
SCLK
DIN
Figure 41. AD5302/AD5312/AD5322 in an Opto-Isolated Interface
10kΩ
10kΩ
10kΩ
REGULATOR
V
V
V
DD
DD
DD
5V
AD5302/AD5312/
SCLK
SYNC
DIN
GND
AD5322
V
DD
V
V
V
V
OUT
REF
OUT
10µF
REF
A
B
A
B
0.1µF
Rev. D | Page 19 of 24
The 74HC139 is used as a 2-to-4 line decoder to address any of
the DACs in the system. To prevent timing errors from occurring,
the enable input should be brought to its inactive state while the
coded address inputs are changing state. Figure 42 shows a
diagram of a typical setup for decoding multiple AD5302/
AD5312/AD5322 devices in a system.
ADDRESS
AD5302/AD5312/AD5322 AS A DIGITALLY
PROGRAMMABLE WINDOW DETECTOR
Figure 43 shows a digitally programmable upper-/lower-limit
detector using the two DACs in the AD5302/AD5312/AD5322.
The upper and lower limits for the test are loaded to DAC A
and DAC B, which, in turn, set the limits on the CMP04. If the
signal at the V
an LED indicates the fail condition.
V
Figure 42. Decoding Multiple AD5302/AD5312/AD5322 Devices in a System
ENABLE
REF
SYNC
SCLK
CODED
5V
SCLK
DIN
DIN
Figure 43. Window Detector Using AD5302/AD5312/AD5322
0.1µF
V
V
DIN
SCLK
SYNC
AD5302/AD5312/
REF
REF
1G
1A
1B
A
B
IN
74HC139
AD5322
input is not within the programmed window,
DGND
V
V
10µF
GND
DD
CC
V
1Y0
1Y1
1Y2
1Y3
V
V
DD
OUT
OUT
AD5302/AD5312/AD5322
A
B
V
IN
CMP04
1/2
SYNC
DIN
SCLK
SYNC
DIN
SCLK
SYNC
DIN
SCLK
SYNC
DIN
SCLK
AD5302/AD5312/AD5322
AD5302/AD5312/AD5322
AD5302/AD5312/AD5322
AD5302/AD5312/AD5322
PASS/FAIL
1kΩ
1/6 74HC05
FAIL
1kΩ
PASS