AD5302 Analog Devices, AD5302 Datasheet - Page 8

• Manufacturer Part Number: AD5302
• Manufacturer: Analog Devices

Specifications of AD5302

• Resolution (bits): 8bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5302/AD5312/AD5322
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
LDAC
V
V
V
V
V
SYNC
SCLK
DIN
GND
DD
REF
REF
OUT
OUT
B
A
A
B
Description
Active Low Control Input. This pin transfers the contents of the input registers to their respective DAC registers.
Pulsing LDAC low allows either or both DAC registers to be updated if the input registers have new data. This
allows simultaneous updating of both DAC outputs.
Power Supply Input. The parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND.
Reference Input Pin for DAC B. This is the reference for DAC B. It can be configured as a buffered or an
unbuffered input, depending on the BUF bit in the control word of DAC B. It has an input range of 0 V to V
unbuffered mode and 1 V to V
Reference Input Pin for DAC A. This is the reference for DAC A. It can be configured as a buffered or an
unbuffered input depending on the BUF bit in the control word of DAC A. It has an input range of 0 V to V
unbuffered mode and 1 V to V
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling
edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts
as an interrupt and the write sequence is ignored by the device.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.
Serial Data Input. This device has a 16-bit input shift register. Data is clocked into the register on the falling
edge of the serial clock input. The DIN input buffer is powered down after each write cycle.
Ground Reference Point for All Circuitry on the Part.
V
V
V
LDAC
REF
OUT
REF
V
DD
B
A
A
Figure 5. Pin Configuration
DD
DD
1
2
3
4
5
in buffered mode.
in buffered mode.
Rev. D | Page 8 of 24
(Not to Scale)
AD5302/
AD5312/
AD5322
TOP VIEW
10
9
8
7
6
GND
DIN
SCLK
SYNC
V
OUT
B
DD
DD
in
in