STA020D STMicroelectronics, STA020D Datasheet
STA020D
Specifications of STA020D
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STA020D Summary of contents
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... PARITY BITS AND CRC CODES GENERATED TRANSPARENT MODE ALLOWS DIRECT CONNECTION OF STA020D AND STA120 DESCRIPTION The STA020D is a monolithic CMOS device which encodes and transmits audio data according to the AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340 inter- face standards. It supports 96kHz sample rate op- eration ...
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STA020 ABSOLUTE MAXIMUM RATINGS Symbol V DC Power Supply D+ V Digital Input Voltage IND T Ambient Operating Temperature (power applied) amb T Storage Temperature stg RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground) Symbol Parameter ...
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PIN DESCRIPTION (continued) N° Pin 7 FSYNC Frame Sync. Delineates the serial data and may indicate the particular channel, left or right and may be an input or output. The format is based on M0, M1 and M2 pins. 8 ...
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... TRNPT/FC1 Transparent Mode/Frequency Control 1. In professional mode, setting TRNPT low selects normal operation & CBL is an output. Setting TRNPT high, allows the STA020D to be connected directly to an STA120. In transparent mode, CBL is an input & MCK must be at 256 Fs. In consumer mode, FC0 and FC1 are encoded versions of channel status bits 24 and 25 ...
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... AES/EBU, IEC 958, S/PDIF, and EIAJ CP-340 interface standards. The chip accepts audio and con- trol data separately; multiplex and biphase-mark encode the data internally and drive it, directly or through a transformer transmission line. The STA020D has dedicated pins for the most important control bits and a serial input port for the C, U and V bits. Line Drivers The differential line drivers for STA020D are low skew, low impedance, differential outputs capable of driv- ing 110Ohm transmission lines ...
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... FSYNC to delineate samples. Formats 5 and 6 require a minimum of 16- or 18-bit audio words respectively. In all formats other than 5 and 6, the STA020D can accept any word length from bits by adding leading zeros in format 7 and trailing zeros in the other formats restricting the number of SCK periods between active edges of FSYNC to the sample word length ...
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Figure 3. Audio Serial Port Formats. FORMAT 0: FSYNC(out) SCK(out) SDATA(in) FORMAT 1: FSYNC(in) SCK(in) SDATA(in) FORMAT 2: FSYNC(in) SCK(in) SDATA(in) FORMAT 3: (RESERVED) FORMAT 4: FSYNC(in) SCK(in) SDATA(in) FORMAT 5: FSYNC(in) SCK(in) SDATA(in) FORMAT 6: FSYNC(in) SCK(in) SDATA(in) FORMAT ...
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STA020 RST and CBL (TRNPT is low) When RST goes low, the differential line drivers are set to ground. In order to properly synchronize the ST020 to the audio serial port, the transmit timing counters, which include CBL, are not ...
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... Frame synchronization of digital audio signals input to and output from a piece of equipment must be within ±5%. The transparent mode of the STA020D is selected by setting TRNPT, pin 24, high. In this mode, the CBL pin becomes an input, allowing direct connection of the outputs of the STA120 to the inputs of the STA020D as shown in Figure 18 ...
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STA020 Table 3. Sample Frequency Encoding FC1 FC0 Figure 5. Transparent Mode Interface. Figure 6. Block Diagram - Professional Mode SDATA SERIAL 6 SCK PORT 7 LOGIC FSYNC ...
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Figure 7. Block Diagram - Consumer Mode SDATA SERIAL 6 SCK PORT 7 LOGIC FSYNC REGISTERS 9 V MUX PRO FC0 FC1 C2 C3 +3. ...
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STA020 mm DIM. MIN. TYP. MAX. A 2.35 2.65 0.093 A1 0.10 0.30 0.004 B 0.33 0.51 0.013 C 0.23 0.32 0.009 (1) 15.20 15.60 0.598 D E 7.40 7.60 0.291 e 1.27 H 10.0 10.65 0.394 h 0.25 0.75 ...
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REVISION HISTORY Date Revision 14-Oct-2002 5 Technical Migration from ST-PRESS to EDOCS 26-Apr-2010 6 Major revision for revalidation process Changes STA020 13/14 ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...