ADP5034 Analog Devices, ADP5034 Datasheet - Page 23

• Manufacturer Part Number: ADP5034
• Description: Dual 3 MHz, 1200mA Buck Regulator with Two 300 mA LDOs
• Manufacturer: Analog Devices

Data Sheet
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by
where:
C
C
For the ADP5034, the total of ( C
approximately 150 pF.
The transition losses occur because the P-channel power
MOSFET cannot be turned on or off instantaneously, and the
SW node takes some time to slew from near ground to near
V
loss is calculated by
where t
switching node, SW. For the ADP5034, the rise and fall times of
SW are in the order of 5 ns.
If the preceding equations and parameters are used for estimat-
ing the converter efficiency, it must be noted that the equations
do not describe all of the converter losses, and the parameter
values given are typical numbers. The converter performance
also depends on the choice of passive components and board
layout; therefore, a sufficient safety margin should be included
in the estimate.
LDO Regulator Power Dissipation
The power loss of a LDO regulator is given by
where:
I
V
respectively.
I
Power dissipation due to the ground current is small and it
can be ignored.
The total power dissipation in the ADP5034 simplifies to
LOAD
GND
GATE-P
GATE-N
IN
OUT1
and V
is the ground current of the LDO regulator.
P
P
P
P
is the load current of the LDO regulator.
(and from V
SW
TRAN
DLDO
D
is the P-MOSFET gate capacitance.
is the N-MOSFET gate capacitance.
RISE
= P
= ( C
OUT
= V
= [( V
and t
DBUCK1
GATE-P
are input and output voltages of the LDO,
IN1
FALL
IN
× I
+ P
− V
OUT1
+ C
OUT1
are the rise time and the fall time of the
DBUCK2
OUT
GATE-N
to ground). The amount of transition
× ( t
) × I
+ P
) × V
RISE
LOAD
DLDO1
+ t
GATE-P
IN1
] + ( V
FALL
2
+ P
× f
) × f
+ C
DLDO2
SW
IN
× I
SW
GATE-N
GND
) is
)
(10)
(11)
(12)
(13)
Rev. A | Page 23 of 28
JUNCTION TEMPERATURE
In cases where the board temperature, T
thermal resistance parameter, θ
junction temperature rise. T
the formula
The typical θ
35°C/W (see Table 6). A very important factor to consider is
that θ
JEDEC standard, and real applications may use different sizes
and layers. It is important to maximize the copper used to remove
the heat from the device. Copper exposed to air dissipates heat
better than copper used in the inner layers. The exposed pad
should be connected to the ground plane with several vias.
If the case temperature can be measured, the junction
temperature is calculated by
where T
thermal resistance provided in Table 6.
When designing an application for a particular ambient
temperature range, calculate the expected ADP5034 power
dissipation (P
Equation 8 to Equation 13. From this power calculation, the
junction temperature, T
The reliable operation of the converter and the two LDO regulators
can be achieved only if the estimated die junction temperature of
the ADP5034 (Equation 14) is less than 125°C. Reliability and
mean time between failures (MTBF) are highly affected by increas-
ing the junction temperature. Additional information about
product reliability can be found from the ADI Reliability Handbook ,
which can be found at
T
T
JA
J
J
= T
= T
is based on a 4-layer 4 in × 3 in, 2.5 oz copper, as per
C
is the case temperature and θ
A
C
+ ( P
+ ( P
JA
D
) due to the losses of all channels by using the
value for the 24-lead, 4 mm × 4 mm LFCSP is
D
D
× θ
× θ
JC
JA
www.analog.com/reliability_handbook
)
)
J
, can be estimated using Equation 14.
J
is calculated from T
JA
, can be used to estimate the
JC
A
is the junction-to-case
, is known, the
A
ADP5034
and P
D
using
(14)
(15)
.