ADP1043A Analog Devices, ADP1043A Datasheet
ADP1043A
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ADP1043A Summary of contents
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... Trademarks and registered trademarks are the property of their respective owners. Digital Controller for Isolated Power Supply Applications GENERAL DESCRIPTION The ADP1043A is a secondary side power supply controller IC designed to provide all the functions that are typically needed in an ac-to-dc or isolated dc-to-dc control application. The ADP1043A is optimized for minimal component count, maximum flexibility, and minimum design time ...
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... ADP1043A TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Typical Application Circuit ............................................................. 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5 Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...................................................................... 8 Soldering ........................................................................................ 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 11 Theory of Operation ...................................................................... 12 Current Sense .............................................................................. 12 Voltage Sense and Control Loop .............................................. 13 ADCs ...
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... Light Load Operation (Burst Mode) ........................................ 66 OUTAUX in Resonant Mode .................................................... 66 Protections in Resonant Mode .................................................. 66 REVISION HISTORY 10/09—Revision 0: Initial Version Resonant Mode Register Descriptions ..................................... 67 Outline Dimensions ........................................................................ 71 Ordering Guide ........................................................................... 71 Rev Page ADP1043A ...
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... GUI is available that provides all the necessary software to program the ADP1043A. For more information about the GUI, contact Analog Devices, Inc., for the latest software and a user guide. The ADP1043A operates from a single 3.3 V supply and is specified from −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM ADC ...
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... VS3+ to VS3− From 0% to 100% of input voltage range From 10% to 90% of input voltage range From 900 mV to 1.1 V Register 0x2C[ Relative to nominal voltage ( VS1 Register 0x2C[ Relative to nominal voltage ( VS2 and VS3 Rev Page ADP1043A Min Typ Max Unit 3.1 3.3 3 ...
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... ADP1043A Parameter Symbol CURRENT SENSE 1 (CS1 PIN) Input Voltage Range V IN Sampling Frequency f SAMP Current Sense Measurement Accuracy Current Sense Measurement Resolution CS1 Fast OCP Threshold CS1 Fast OCP Speed CS1 Accurate OCP DC Accuracy CS1 Accurate OCP Speed Leakage Current CURRENT SENSE 2 (CS2+, CS2− ...
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... Test Conditions/Comments When RTD = 10 kΩ When RTD = 100 kΩ When RTD = 10 kΩ 3 85° 85°C as per JEDEC Standard 22, Method A117. Retention lifetime derates with junction temperature. J Rev Page ADP1043A Min Typ Max Unit −0.5 +0.5 % FSR −7.75 +7.75 mV − FSR − ...
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... SOLDERING 150° important to follow the correct guidelines when laying out the PCB footprint for the ADP1043A and when soldering the 240°C part onto the PCB. The AN-772 Application Note discusses this 260°C topic in detail (see www.analog.com). ...
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... V. The resistor divider on this input must have a tolerance specification of 0.5% or better to allow for trimming. 2 AGND Analog Ground. This pin is the ground for the analog circuitry of the ADP1043A. Star connect to DGND. 3 VS1 Local Voltage Sense Input. This signal is referred to PGND. Input to a high frequency Σ-Δ ADC. Nominal voltage at this pin should ...
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... The resistor divider on this input must have a tolerance specification of 0.5% or better to allow for trimming. EP Exposed The ADP1043A has an exposed thermal pad on the underside of the package. For increased reliability of the Pad solder joints and maximum thermal capability recommended that the pad be soldered to the PCB ground plane. ...
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... Figure 8. CS2 ADC Accuracy vs. Temperature (from 200 mV) 1.35 1.30 1.25 1.20 1.15 1.10 MAX SPEC 1.05 – Figure 9. CS1 Fast OCP Threshold vs. Temperature Rev Page ADP1043A MEAN MIN MAX MIN SPEC MAX SPEC MIN_N10% MAX_P10% – TEMPERATURE (°C) MEAN MIN MAX ...
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... ADP1043A THEORY OF OPERATION CURRENT SENSE The ADP1043A has two individual current sense inputs: CS1 and CS2±. These inputs sense, protect, and control the output current and the share bus information. They can be calibrated to remove any errors due to external components. CS1 Operation (CS1) CS1 is typically used for the monitoring and protection of the primary side current ...
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... VS2 sense point on the power rail needs an external resistor divider to bring the nominal common-mode signal the VS2 pin (see Figure 13). The resistor divider is necessary because the ADP1043A VS2 ADC input range 1.55 V. 12V This divided-down signal is internally fed into an ADC. The ...
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... Register 0x60 to Register 0x63. The other filter, called the light load mode filter, is controlled by programming Register 0x64 to Register 0x67. The ADP1043A uses the light load mode filter only when the modulation is below the load current threshold (programmed through Register 0x3B). ...
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... This ensures that power flows only out of the power supply and that the unit can be hot-swapped. The OrFET circuit can be used only when the ADP1043A is connected to a sense resistor on the low side. The OrFET circuit is not guaranteed for operation with high-side current sensing. ...
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... ADP1043A Accurate OrFET control also uses the reverse voltage across the CS2+ and CS2− pins to disable the OrFET (see Figure 16). If the voltage difference between CS2+ and CS2− is greater than 0 mV, the OrFET is disabled. The accurate OrFET circuit is more accu- rate, but it is slower than the fast OrFET circuit ...
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... CS2 VS1 CH1 2.00V CH2 2.00V M200.0ms A CH4 CH3 2.00A CH4 10.0V Green Is OrFET Control Signal; Blue Is Load Current) VS3 VS1 OrFET CS2 CH1 2.00V CH2 2.00V M5.0ms A CH4 CH3 2.00A CH4 10.0V Green Is OrFET Control Signal; Blue Is Load Current) ADP1043A 7.5mV 8.3mV ...
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... The EEPROM contents are then downloaded to the registers. The download takes an additional 25 μs (approximately). After the EEPROM download, the ADP1043A is ready for operation. If the ADP1043A is programmed to power up at this time, the soft start ramp begins. VDD/VCORE OVLO The ADP1043A has built-in overvoltage protection (OVP) on its supply rails ...
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... Fault Condition During Soft Start If a CS1 fast OCP fault condition occurs during soft start, the entire soft start routine is reset, and the ADP1043A begins another soft start routine. All other fault flags are ignored during soft start. Soft Start Routine ...
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... If a new ADP1043A is hot-swapped onto an existing digital share bus, it waits to begin sharing until the next frame. The new ADP1043A monitors the share bus until it sees a stop bit, which designates the end of a share frame. It then performs synchronization with the other ADP1043A devices during the next start bit. The digital share bus frame is shown in Figure 24. CS2– ...
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... The digital word that represents the current information is eight bits long. The ADP1043A takes the eight MSBs of the CS1 or CS2 reading (whichever the user chooses as the current share signal) and uses this reading as the digital word. When read, the share bus value at any given time is equal to the CS1 or CS2 current reading (see Figure 26) ...
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... The limits for the fault conditions are programmable. The ADP1043A has an extensive set of flags that are set when certain thresholds or limits are exceeded. These thresholds and limits are described in the Fault Registers section. ...
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... If a flag is set to be ignored, it does not appear in the first flag register. EXTERNAL FLAG INPUT (FLAGIN PIN) The FLAGIN pin can be used to send an external fault signal into the ADP1043A. The reaction to this flag can be programmed in the same way as the internal flags. TEMPERATURE READINGS (RTD PIN) ) The RTD pin is set up for use with an external 100 kΩ ...
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... ADP1043A OVERCURRENT PROTECTION (OCP) The ADP1043A has several OCP functions. CS1 and CS2 have individual OCP circuits to provide both primary and secondary side protection. CS1 has two protection circuits: CS1 fast OCP and CS1 accurate OCP (see Figure 29). CS1 fast OCP is an analog comparator. ...
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... OCP × 90% Figure 30. Constant Current Mode (V OVERVOLTAGE PROTECTION (OVP) The ADP1043A has two OVP circuits. If the output voltage at the VS1, VS2, or VS3 pin exceeds the programmable threshold for that pin, that OVP flag is set; the response to that flag can be programmed. VS1 has one OVP circuit. VS2 and VS3 share the other OVP circuit ...
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... OUTB is decreased and OUTD is increased. LOAD LINE The ADP1043A can optionally introduce a digital load line into the power supply. This option is programmed in the load line impedance register (Register 0x36). This feature can be used for advanced current sharing techniques ...
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... CS2 Gain Trim After performing the offset trim, perform the gain trim to remove any mismatch that is introduced by the sense resistor tolerance. The ADP1043A can trim for sense resistors with a tolerance better. 1. Apply a known current (I 2 ...
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... IC in protective resin after this curing to ensure that any impurities cannot contaminate the IC. CS2 + and CS2− The routing of the traces from the sense resistor to the ADP1043A should be laid out in parallel to each other. The traces should also be kept close together and as far from the switch nodes as possible. VS3+ and VS3− ...
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... ADD pin directly to VDD) 2 General I C Timing The ADP1043A has a timeout feature to protect against a fault 2 condition on the SDA line. The I C interface monitors the SDA line and stays low for time 0.65 ms < t_low < 1.3 ms, the interface is reset and waits for another start condition ...
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... ACK. BY ADP1043A ADDRESS POINTER REGISTER BYTE Figure 33. Writing to the Address Pointer Register Only R ACK. BY ADP1043A DATA BYTE FROM ADP1043A Figure 34. Reading Data from a Previously Selected Register Rev Page ACK. BY ADP1043A FRAME ...
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... Write: DevAddr=0x57 AddrPtr=0x7C Data=0x63 BYTE 62 BYTE 63 Write: DevAddr=0x57 AddrPtr=0x7D Data=0x1E Write: DevAddr=0x57 AddrPtr=0x7E Data=0xAA BYTE 62 BYTE 63 Read Example BYTE 62 BYTE 63 Read data from Page 10, Row 7, Column 62 of the ADP1043A Address 0x50. BYTE 62 BYTE 63 Read: DevAddr=0x50 BYTE 62 BYTE 63 Read: DevAddr=0x50 ...
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... EEPROM to the registers at startup. SOFTWARE GUI A free software GUI is available for programming and configu- ring the ADP1043A. The GUI is designed to be intuitive to power supply designers and dramatically reduces power supply design and development time. The software includes filter design and power supply PWM topology windows. The GUI is also an information center, displaying the status of all readings, monitoring, and flags on the ADP1043A ...
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... OUTAUX rising edge timing (OUTAUX pin) 0x5A OUTAUX rising edge setting (OUTAUX pin) 0x5B OUTAUX falling edge timing (OUTAUX pin) 0x5C OUTAUX falling edge setting (OUTAUX pin) 0x5D OUTx and SRx pin disable setting 0x5E Password lock Rev Page ADP1043A ...
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... ADP1043A Address Name Digital Filter Programming Registers 0x5F Soft start digital filter LF gain setting 0x60 Normal mode digital filter LF gain setting 0x61 Normal mode digital filter zero setting 0x62 Normal mode digital filter pole setting 0x63 Normal mode digital filter HF gain setting ...
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... The soft start filter is in use. 0 External flag R The external flag pin (FLAGIN) is set interface unless the fault is still present recommended that the latched 2 C interface stays functional, but a PSON Rev Page ADP1043A Register Action None 0x30 None 0x2D None None 0x5D ...
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... ADP1043A Table 11. Register 0x03—Fault Register 4 and Register 0x07—Latched Fault Register Fault Normal Operation) Bits Name R/W 7 Reserved R 6 Modulation R 5 Address R 4 Light load mode R 3 Reserved R 2 ACSNS R 1 CRC fault R 0 EEPROM unlocked R Table 12. Register 0x08 to Register 0x0D—Fault Configuration Registers ...
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... Setting this bit means that the CS1 accurate OCP flag is ignored until the end of the soft start ramp time. Setting this bit means that the CS1 fast OCP flag is ignored until the end of the soft start ramp time. Rev Page ADP1043A ...
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... This register contains the 16-bit input voltage information. Because the input voltage is normally on the other side of the isolation barrier from the ADP1043A, the part does not directly sense the input voltage. The input voltage is defined as the VS1 voltage divided by the PWM modulation. To read the input voltage information, this register must be read using two consecutive read operations ...
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... input signal on CS2, the value in this register is 30 mV/30.52 μV = 982 (0x3D6). If the nominal voltage range is from 37.5 mV, the LSB step size is 15.26 μ input signal on CS2, the value in this register is 30 mV/15.26 μV = 1966 (0x7AE). Reserved. Rev Page ADP1043A ...
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... ADP1043A Table 24. Register 0x19—CS2 × VS3 Value (Output Power) Bits Name R/W [15:0] Output power value R Table 25. Register 0x1A—RTD Temperature Value Bits Name R/W [15:4] Temperature value R [3:0] Reserved R Table 26. Register 0x1D—Share Bus Value Bits Name R/W [7:0] Share bus value R Table 27. Register 0x1E—Modulation Value ...
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... This register calibrates the secondary side (CS2) current sense gain. It calibrates for errors in the sense resistor. This is Step 2 in the CS2 Gain Trim section. Rev Page ADP1043A LSB Step Size (μV) 15.26 30.52 61.04 ...
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... ADP1043A Table 32. Register 0x24—CS2 Analog Offset Trim Bits Name R/W 7 CS2 high side R/W 6 Offset polarity R/W [5:0] CS2 offset trim R/W Table 33. Register 0x25—CS2 Digital Trim Bits Name R/W [7:0] CS2 digital trim R/W Table 34. Register 0x26—CS2 Accurate OCP Limit Bits Name R/W [7:0] CS2 accurate OCP R/W Table 35. Register 0x27— ...
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... Description Set these bits to 000 for normal operation negative gain is introduced positive gain is introduced. This register calibrates the RTD ADC gain. It calibrates for errors in the ADC. This value allows ±12% trim to be realized. Rev Page ADP1043A ...
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... If the soft stop feature is enabled, a soft stop occurs even if a fault flag causes a shutdown event. This may cause the ADP1043A to continue switching for longer than desired. The user needs to consider this factor before enabling the soft stop feature soft stop time is the same as the soft start time. ...
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... Nominal + 50% Reserved. Setting this bit enables pulse skipping mode. If the ADP1043A requires a duty cycle lower than the modulation low limit, pulse skipping is enabled. These bits set the minimum allowed modulation that is applied to a PWM output. The value is a percentage of the switching period. If the modulation calculated is lower than this limit, pulse skipping can be enabled ...
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... ADP1043A Table 44. Register 0x30—OrFET Bits Name R/W [7:6] Accurate OrFET R/W threshold [5:4] OrFET enable R/W threshold [3:2] Fast OrFET R/W threshold 1 Fast OrFET R/W debounce 0 Fast OrFET bypass R/W VOLTAGE SENSE REGISTERS Table 45. Register 0x31—VS3 Voltage Setting (Remote Voltage) Bits Name R/W [7:0] VS3 voltage setting R/W Table 46. Register 0x32—VS1 Overvoltage Limit (OVP) ...
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... Setting these bits to 31 gives an OVP limit of 145.3% of the nominal VS2/VS3 voltage. When this bit is set, the ADP1043A regulates from the VS3 node at all times. When this bit is not set, the ADP1043A uses the VS1 voltage as the regulating point during soft start and when the OrFET is disabled ...
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... ADP1043A Table 49. Register 0x35—Line Impedance Limit Bits Name R/W [7:0] Line impedance R/W limit Table 50. Register 0x36—Load Line Impedance Bits Name R/W [7:4] Reserved R/W 3 Enable R/W [2:0] Load line R/W Table 51. Register 0x38—VS1 Trim Bits Name R/W 7 Trim polarity R/W [6:0] VS1 trim R/W Table 52. Register 0x39—VS2 Trim Bits ...
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... This register contains the ID code for the device. This value is hardwired to 0x43 to represent the ADP1043A. Bit 1 Bit Full Load 37.5 mV Setting 1 8 11.5 Rev Page ADP1043A Threshold for Each Nominal CS2 Setting (mV Setting 150 mV Setting 6.3 12.5 9.8 19.5 13.3 26.5 16 ...
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... ADP1043A PWM AND SYNCHRONOUS RECTIFIER TIMING REGISTERS Figure 36 and Table 58 to Table 88 describe the implementation and programming of the seven PWM signals that are output from the ADP1043A. In general recommended that t SYNC RECT 1 (SR1) SYNC RECT 2 (SR2) Table 58. Register 0x3F—OUTAUX Switching Frequency Setting ...
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... Rev Page ADP1043A Bit 1 Bit 0 Frequency (kHz 115 120 125 130 135 142 148 156 164.5 ...
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... ADP1043A Bits Name R/W [5:0] Switching frequency R/W Description Bit 5 Bit 4 Bit 3 Bit ...
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... Increase of PWM modulation moves positive sign. Increase of PWM modulation moves t Reserved. These bits should be set to 00 for normal operation. Rev Page ADP1043A time. This value is always used with 1 time. Each LSB 1 time. This value is always used with the eight 1 time ...
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... ADP1043A Table 66. Register 0x47—OUTB Falling Edge Timing (OUTB Pin) Bits Name R/W [7:0] t R/W 4 Table 67. Register 0x48—OUTB Falling Edge Setting (OUTB Pin) Bits Name R/W [7: Modulate enable R sign R/W 4 [1:0] Reserved R/W Table 68. Register 0x49—OUTC Rising Edge Timing (OUTC Pin) Bits Name ...
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... SR1 and SR2, along with OUTB and OUTD. When this bit is set, the volt-second balance modulation is applied to the rising edge of SR1 and SR2. Reserved. This bit should be set to 0 for normal operation. Rev Page ADP1043A time. This value is always used with the 7 time. Each LSB corresponds 7 time ...
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... ADP1043A Table 78. Register 0x53—SR1 Falling Edge Timing (SR1 Pin) Bits Name R/W [7:0] t R/W 10 Table 79. Register 0x54—SR1 Falling Edge Setting (SR1 Pin) Bits Name R/W [7: Modulate enable R sign R soft start setting R soft start enable R/W Table 80. Register 0x55—SR2 Rising Edge Timing (SR2 Pin) ...
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... PWM timing while the power supply is on. This bit also latches in any changes made to Register 0x31 (VS3 voltage setting). Rev Page ADP1043A time. This value is always used with the top 13 time. Each LSB corresponds to 13 time ...
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... ADP1043A Table 89. Register 0x5E—Password Lock Bits Name R/W [7:0] Password W DIGITAL FILTER PROGRAMMING REGISTERS 100Hz Table 90. Register 0x5F—Soft Start Digital Filter LF Gain Setting Bits Name R/W [7:2] Reserved R/W [1:0] Soft start filter gain R/W Table 91. Register 0x60—Normal Mode Digital Filter LF Gain Setting Bits Name ...
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... This register determines the position of the final 0. See Figure 37. Description This register determines the position of the final pole. See Figure 37. Description This register determines the high frequency gain of the loop response. Programmable over range. Each LSB corresponds to a 0.3 dB increase. See Figure 37. Rev Page ADP1043A ...
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... ADP1043A ADAPTIVE DEAD TIME REGISTERS Table 99. Register 0x68—Dead Time Threshold Bits Name R/W [7:3] Reserved R/W [2:0] Adaptive dead time R/W threshold Table 100. Register 0x69—Dead Time 1 Bits Name R polarity R/W 1 [6:4] t offset R polarity R/W 2 [2:0] t offset R/W 2 Description Reserved. This value determines the adaptive dead time threshold. Below this threshold, the offsets from Register 0x69 to Register 0x6F are introduced ...
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... This value determines the t offset from the nominal timing. 6 Bit 2 Bit 1 Bit 0 Offset (ns Rev Page ADP1043A ...
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... ADP1043A Table 103. Register 0x6C—Dead Time 4 Bits Name R polarity R/W 7 [6:4] t offset R polarity R/W 8 [2:0] t offset R/W 8 Table 104. Register 0x6D—Dead Time 5 Bits Name R polarity R/W 9 [6:4] t offset R polarity R/W 10 [2:0] t offset R/W 10 Description 0 = positive polarity negative polarity. This value determines the t offset from the nominal timing ...
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... This value determines the t offset from the nominal timing. 14 Bit 2 Bit 1 Bit 0 Offset (ns Rev Page ADP1043A ...
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... ADP1043A EEPROM REGISTERS Table 107. Register 0x7B—EEPROM Restore Factory Default Register Settings Bits Name R/W [7:0] EEPROM restore factory R/W default settings Table 108. Register 0x7C—EEPROM X Address Bits Name R/W 7 Reserved R/W [6:0] EEPROM X address R/W Table 109. Register 0x7D—EEPROM Y Address Bits Name R/W [7:6] Reserved R/W [5:0] EEPROM Y address R/W Table 110. Register 0x7E— ...
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... Figure 40. SR1 and SR2 PWM Timing Diagram in Resonant Mode whereas A B Following is an example of how the ADP1043A can be used in a series resonant topology and also achieve control of the synchronous rectifiers. The V control the SR signals. The ACSNS pin is connected to the divided-down SR2 V information for both synchronous rectifiers (see Figure 41) ...
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... PWM mode (see the Soft Start section). LIGHT LOAD OPERATION (BURST MODE) To control the converter at very light load, the ADP1043A can operate in burst mode. Burst mode can be enabled or disabled using Bits[7:6] of Register 0x4A. When the desired switching frequency is higher than the burst mode threshold, the part enters burst mode ...
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... Bits[7:4] of Register 0x44 are set to 0xF (15 decimal), the maximum switching cycle is (160 × 15) × 12.875 μs, and the lowest switching frequency limit is 1/12.875 μs = 77.7 kHz. Reserved. Rev Page ADP1043A Bit 2 Bit 1 Bit 0 Δt (ns) ...
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... ADP1043A Table 116. Register 0x45—OUTB Rising Edge Dead Time in Resonant Mode Bits Name R/W [7:0] Δt (rising edge dead R/W 3 time of OUTB) Table 117. Register 0x46—Highest Switching Frequency Limit Setting (Minimum Switching Cycle in Resonant Mode) Bits Name R/W [7:0] Highest frequency R/W Table 118. Register 0x47—OUTB Falling Edge Dead Time in Resonant Mode ...
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... Rev Page ADP1043A . When the value is from 0x80 to 0xFF, B Bit 2 Bit 1 Bit 0 Δ trailing … … … … 635 ns trailing ...
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... ADP1043A Table 124. Register 0x4F—OUTD Falling Edge Dead Time in Resonant Mode Bits Name R/W [7:0] Δt (falling edge dead R/W 8 time of OUTD) Table 125. Register 0x51—SR1 Rising Edge Dead Time in Resonant Mode Bits Name R/W [7:0] Δt (rising edge dead R/W 9 time of SR1) Table 126. Register 0x53—SR1 Falling Edge Dead Time in Resonant Mode ...
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... Lead Frame Chip Scale Package [LFCSP_VQ] Rev Page 0.60 MAX PIN 1 INDICATOR 3.25 EXPOSED PAD 3.10 SQ (BOTTOM VIEW) 2. 0.25 MIN 3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option CP-32-2 ADP1043A ...
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... ADP1043A NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08501-0-10/09(0) Rev Page ...