ADP1043A Analog Devices, ADP1043A Datasheet - Page 57

• Manufacturer Part Number: ADP1043A
• Description: Digital Controller for Isolated Power Supply Applications
• Manufacturer: Analog Devices

Table 84. Register 0x59—OUTAUX Rising Edge Timing (OUTAUX Pin)
Bits
[7:0]
Table 85. Register 0x5A—OUTAUX Rising Edge Setting (OUTAUX Pin)
Bits
[7:4]
3
2
[1:0]
Table 86. Register 0x5B—OUTAUX Falling Edge Timing (OUTAUX Pin)
Bits
[7:0]
Table 87. Register 0x5C—OUTAUX Falling Edge Setting (OUTAUX Pin)
Bits
[7:4]
3
2
1
0
Table 88. Register 0x5D—OUTx and SRx Pin Disable Setting
Bits
7
6
5
4
3
2
1
0
Name
t
Name
t
Modulate enable
t
Regulate with
OUTAUX
Reserved
Name
t
Name
t
Modulate enable
t
Reserved
Name
OUTAUX disable
SR2 disable
SR1 disable
OUTD disable
OUTC disable
OUTB disable
OUTA disable
GO
13
13
13
14
14
14
sign
sign
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
Description
This register contains the eight MSBs of the 12-bit t
four bits of Register 0x5A, which contains the four LSBs of the t
5 ns resolution.
Description
These bits contain the four LSBs of the 12-bit t
bits of Register 0x59, which contains the eight MSBs of the t
resolution.
1 = PWM modulation acts on the t
0 = no PWM modulation of the t
1 = negative sign. Increase of PWM modulation moves t
0 = positive sign. Increase of PWM modulation moves t
Reserved. Set these bits to 00 for normal operation.
Description
This register contains the eight MSBs of the 12-bit t
four bits of Register 0x5C, which contains the four LSBs of the t
5 ns resolution.
Description
These bits contain the four LSBs of the 12-bit t
bits of Register 0x5B, which contains the eight MSBs of the t
resolution.
1 = PWM modulation acts on the t
0 = no PWM modulation of the t
1 = negative sign. Increase of PWM modulation moves t
0 = positive sign. Increase of PWM modulation moves t
1 = control loop PWM modulation is regulated by OUTAUX. When this bit is set, the CS1 blanking
signal is synchronized with OUTAUX.
0 = control loop PWM modulation is regulated by OUTA, OUTB, OUTC, OUTD, SR1, and SR2
(normal mode).
Reserved. Set this bit to 0 for normal operation.
Description
Setting this bit disables the OUTAUX output.
Setting this bit disables the SR2 output.
Setting this bit disables the SR1 output.
Setting this bit disables the OUTD output.
Setting this bit disables the OUTC output.
Setting this bit disables the OUTB output.
Setting this bit disables the OUTA output.
This bit latches in all registers from Address 0x3F to Address 0x5D. This bit prevents the PWM
timing from being temporarily incorrect, if changing PWM timing while the power supply is on.
This bit also latches in any changes made to Register 0x31 (VS3 voltage setting).
Rev. 0 | Page 57 of 72
13
14
13
edge.
14
edge.
edge.
edge.
13
14
time. This value is always used with the eight
time. This value is always used with the eight
13
14
time. This value is always used with the top
time. This value is always used with the top
13
14
13
14
left.
left.
right.
right.
13
14
time. Each LSB corresponds to 5 ns
time. Each LSB corresponds to 5 ns
13
14
time. Each LSB corresponds to
time. Each LSB corresponds to
ADP1043A