ADP1043A Analog Devices, ADP1043A Datasheet - Page 19

• Manufacturer Part Number: ADP1043A
• Description: Digital Controller for Isolated Power Supply Applications
• Manufacturer: Analog Devices

SOFT START
A dedicated filter is used during soft start. The filter is disabled
at the end of the soft start routine, and the voltage loop digital
filter is used.
Fault Condition During Soft Start
If a CS1 fast OCP fault condition occurs during soft start, the
entire soft start routine is reset, and the ADP1043A begins another
soft start routine. All other fault flags are ignored during soft start.
Soft Start Routine
When the user turns on the power supply (enables PSON), the
following soft start procedure occurs:
1.
2.
The PSON signal is enabled at Time t
checks that initial flags are OK. These flags include VDD
OK and GND OK.
The ADP1043A waits for Time t
The length of t
LOOP CONTROLLED FROM VS1
LOOP CONTROLLED FROM VS3
1
is set in Register 0x2C, Bits[4:3].
(VS1 – VS2) VOLTAGE
SOFT START RAMP
V
OUT
GATE SIGNAL
UVP FLAG
VOLTAGE
PGOOD1
PSON
1
before it begins soft start.
0
. The ADP1043A
t
0
Figure 21. Soft Start Timing Diagram
t
1
Rev. 0 | Page 19 of 72
120mV
t
2
3.
4.
5.
6.
The soft start begins to ramp up the power supply voltage
at the start of Time t
The ADP1043A keeps the OrFET gate signal turned off.
The voltage differential across the OrFET increases (VS1 −
VS2) due to the diode conduction of the OrFET. When the
voltage differential reaches the OrFET enable threshold
(Register 0x30, Bits[5:4]), the OrFET gate signal is enabled
at Time t
VS3 instead of VS1.
After the power supply voltage increases above the VS1 UVP
undervoltage limit (Register 0x34, Bits[6:0]), at the end of
Time t
After the UVP flag is reset and if all other PGOOD1 fault
conditions are OK, the PGOOD1 signal waits for Time t
before it is enabled. The length of t
Register 0x2D, Bits[7:4].
t
3
4
, the UVP flag is reset.
3
t
. The ADP1043A begins to regulate voltage from
4
UVP
2
.
t
5
5
is programmable in
ADP1043A
5