TDA7500ATR STMicroelectronics, TDA7500ATR Datasheet
TDA7500ATR
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TDA7500ATR Summary of contents
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FULL SOFTWARE FLEXIBILITY WITH TWO 24X24 BIT DSP CORES SOFTWARE AM/FM, AUDIO AND SOUND- PROCESSING HARDWARE RDS FILTER, DEMODULATOR & DECODER INTEGRATED CODEC (4ADCs, 6DACs) IIC AND SPI CONTROL INTERFACES SPI DEDICATED TO DISPLAY MICRO 6 CHANNEL SERIAL AUDIO INTERFACE ...
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TDA7500A DESCRIPTION (continued C/SPI interface is implemented for control and communication with the main micro. A separate SPI is avail- able to interface the display micro.The DSP cores are integrated with their associated data and program mem- ...
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PIN DESCRIPTION N° Name 1 GND1 2 VDD1 3 TESTEN 4 TESTSE 5 NRESET 6 SCKM/DSP0_GPIO0 7 MISOM/DSP0_GPIO1 8 MOSIM/DSP0_GPIO2 9 SSM/DSP0_GPIO3 10 SCKD/DSP0_GPIO4 11 MISOD/DSP0_GPIO5 12 MISOD/DSP0_GPIO6 13 SSD/DSP0_GPIO7 Type Description Ground pin dedicated to the digital circuitry. Supply ...
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TDA7500A PIN DESCRIPTION (continued) N° Name 14 CLKIN 15 AVDD 16 XTI 17 XTO 18 AGND 19 RDSINT/DSP1_GPIO4 20 RDSARI_SCK/DSP1_GPIO3 21 RDSQAL_SO/DSP1_GPIO2 22 RDSDAT_SI/DSP1_GPIO1 23 RDSCLK_SS/DSP1_GPIO0 24 INT 25 CGND1 26 CVDD1 27 SCRCCD 28 SCRMD 29 DSRA<7> 30 DSRA<6> ...
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PIN DESCRIPTION (continued) N° Name 31 DSRA<5> 32 DSRA<4> 33 DSRA<3> 34 DSRA<2> 35 DSRA<1> 36 DSRA<0> 37 SRA<0> 38 SRA<1> 39 SRA<2> 40 SRA<3> 41 SRA<4> 42 SRA<5> 43 SRA<6> 44 SRA<7> 45 SRA<8> Type Description I/O DSP SRAM ...
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TDA7500A PIN DESCRIPTION (continued) N° Name 46 SRA<9> 47 SRA<10> 48 SRA<11> 49 SRA<12> 50 CGND2 51 CVDD2 52 SRA<13> 53 SRA<14> 54 SRA<15> 55 SRA<16>/DSP0_GPIO8 56 DWR 57 DRD 58 CASALE 59 SDO<2>/SRA<17>/DSP1_GPIO<8> 6/40 Type Description O DSP SRAM ...
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PIN DESCRIPTION (continued) N° Name 60 SDO<2>/SRA<18>/DSP1_GPIO<7> 61 SDO<0>/SRA<19> 62 SDI<2>/SRA<20>/DSP1_GPIO<6> 63 SDI<1>/SRA<21>/RAS/DSP1_GPIO<5> 64 SDI<0>/SRCCDC 65 SCKT 66 LRCKT 67 SCKR 68 LRCKR 69 DBOUT1/DSP1_GPIO10 70 DBIN1/OS10/DSP1_GPIO11 71 DBCK1/OS11/DSP1_GPIO9 72 DBRQN1 73 DBOUT0/DSP0_GPIO10 Type Description O SAI Outputs (Output)/EMI SRAM ...
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TDA7500A PIN DESCRIPTION (continued) N° Name 74 DBIN0/OS00/DSP0_GPIO11 75 DBCK0/OS01/DSP0_GPIO9 76 DBRQN0 77 VDD2 78 GND2 79 ADC<0> 80 ADC<1> 81 ADC<2> 82 ADC<3> 83 S2DREF 84 ADCVDDREF 85 ADCREF<2> 86 ADCREF<1> 87 ADCREF<0> 88 ADCVDD 89 ADCGND 90 DAC<0> ...
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PIN DESCRIPTION (continued) N° Name 96 DACREF<2> 97 DACREF<1> 98 DACREF<0> 99 DACGND 100 DACVDD I/O DEFINITION AND STATUS O: logic low output X: undefined input/output Z: high impedance 1: logic input output Pin Function # 1 GND1 2 VDD1 ...
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TDA7500A I/O DEFINITION AND STATUS (continued) Pin Function # 11 DSPI: MISOD input DSPI: MISOD output DSP0: GPIO5 input DSP0: GPIO5 output 12 DSPI: MOSID input DSPI: MOSID output DSP0: GPIO6 input DSP0: GPIO6 output 13 DSPI: SSD input DSP0 ...
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I/O DEFINITION AND STATUS (continued) Pin Function # 30 EMI SRAM: Data<6> bi-direct 31 EMI SRAM: Data<5> bi-direct 32 EMI SRAM: Data<4> bi-direct 33 EMI SRAM: Data<3> bi-direct EMI SRAM: Data<3> bi-direct 34 EMI SRAM: Data<2> bi-direct EMI SRAM: Data<2> ...
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TDA7500A I/O DEFINITION AND STATUS (continued) Pin Function # 52 EMI SRAM: Add<13> output EMI SRAM: Add<13> output 53 EMI SRAM: Add<14> output EMI SRAM: Add<14> output 54 EMI SRAM: Add<15> output EMI SRAM: Add<15> output 55 EMI SRAM: Add<16> ...
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I/O DEFINITION AND STATUS (continued) Pin Function # 69 DSP1 Debug: DBOUT output DSP1: GPIO10 input DSP1: GPIO10 output 70 DSP1 Debug: DBIN input DSP1 : OS10 output DSP1: GPIO11 input DSP1: GPIO11 output 71 DSP1 Debug: DBCK input DSP1 ...
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TDA7500A I/O DEFINITION AND STATUS (continued) Pin Function # 86 ADC: REF<1> input 87 ADC: REF<0> input 88 ADCVDD 89 ADCGND 90 DAC<0> output 91 DAC<1> output 92 DAC<2> output 93 DAC<3> output 94 DAC<4> output 95 DAC<5> output 96 ...
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PIN CONNECTION (Top view) 1 GND1 2 VDD1 3 TESTEN Test 4 TESTSE 5 NRESET 6 DSP0 GPIO0 SCKM OD 7 DSP0 GPIO1 MISOM IIC/SPI master OD 8 DSP0 GPIO2 MOSIM 9 SSM DSP0 GPIO3 10 SCKD DSP0 GPIO4 OD ...
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TDA7500A OSCILLATOR CHARACTERISTICS Symbol Parameter F Max Oscillator Frequency (XTI) OSC GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter l Low Level Input Current without il pullup device l High Level Input Current without ih pullup device I Tri-state Output leakage without ...
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DSP CORE Symbol Parameter F Maximum DSP clock frequency dsp FM Stereo Decoder Symbol Parameter a_ch Channel Separation THD Total Harmonic Distortion (S+N)/N Signal plus Noise to Noise ratio ADC ELECTRICAL CHARACTERISTCS (T A-Weighted Filter.) Symbol Parameter Input Voltage Dynamic ...
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TDA7500A ADC ELECTRICAL CHARACTERISTCS (T 160KHz.) Symbol Parameter Input Voltage Dynamic Range Sampling rate Dynamic Range SNR DAC PERFORMANCE (T = 25°C, V amb 0dB gain, output load 30k ) Symbol Parameter Output voltage dynamic range Sampling rate Attenuation @ ...
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SAI INTERFACE Figure 1. SAI Timings SDI0-3 LRCKR SCKR (RCKP=0) Timing t Minimum Clock Cycle sckr t SCKR active edge to data out valid dt t LRCK setup time lrs t LRCK hold time lrh t SDI setup time sdid ...
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TDA7500A Figure 3. SAI protocol when RLRS=1; RREL=0; RCKP=1; RDIR=1. Figure 4. SAI protocol when RLRS=0; RREL=0; RCKP=0; RDIR=0. Figure 5. SAI protocol when RLRS=0; RREL=1; RCKP=1; RDIR=0. 20/40 ...
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SPI INTERFACES 10 WORDS MAIN MICRO SPI Symbol t Clock Cycle sclk t Sclk edge to MOSI valid dtr t MISO setup time misosetup t MISO hold time misohold t SCK high time sclkh t SCK high low sclkl t ...
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TDA7500A Debug Port Interface No. 1 DBCK rise time 2 DBCK fall time 3 DBCK Low 4 DBCK High 5 DBCK Cycle Time 6 DBRQN Asserted to DBOUT (ACK) Asserted 7 DBCK High to DBOUT Valid 8 DBCK High to ...
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Figure 9. Debug Port Data I/O to Status Timing. Figure 10. Debug Port Read Timing. Figure 11. Debug Port DBCK Next Command After Read Register Timing. TDA7500A 23/40 ...
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TDA7500A EXTERNAL MEMORY INTERFACE (EMI) DRAM MODE Characteristics Page Mode Cycle Time RAS or RD Assertion to Data Valid CAS Assertion to Data Valid Column Address Valid to Data Valid CAS Assertion to Data Active RAS Assertion Pulse Width (Note ...
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EXTERNAL MEMORY INTERFACE (EMI) SRAM MODE Characteristics Address Valid and CS Assertion Pulse Width Address Valid Assertion Assertion Pulse Width Negation Assertion Negation ...
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TDA7500A Figure 14. DRAM Read Cycle. DRA [8:0] Row address 1 RAS CAS DRD DRD [3:0] Figure 15. DRAM Write Cycle. Row address 1 DRA [8:0] RAS CAS DWR DRD[3:0] 26/40 Column address 2 Column address 1 nibble 1 Column ...
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SAMPLE RATE CONVERTER (44.1KHz) sin sout Symbol Parameter THD+N Total Harmonic Distortion + Noise DR Dynamic Range IPD Interchannel Phase Deviation f Cutoff Frequency c R Pass Band Ripple p R Stopband Attenuation s T Group ...
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TDA7500A TIMING Figure 16. Definition of Timing for the I Symbol Parameter F SCLl clock frequency SCL t Bus free between a STOP and BUF Start Condition t Hold time (repeated) START HD:STA condition. After this period, ...
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FUNCTIONAL DESCRIPTION The TDA7500A IC broken up into two distinct blocks. One block contains the two DSP Cores and their associ- ated peripherals. The other contains the ADC, DAC and the RDS filter, demodulator and decoder. 24-BIT DSP CORE The ...
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TDA7500A I2C and SPI interface XCHG Interface for DSP to DSP communication External Memory Interface (DRAM/SRAM) for time-delay and traffic information Double Debug Port DATA AND PROGRAM MEMORY Both DSP0 and DSP1 have Data and Program memories attached to them. ...
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Figure 17. DSP1 and DSP0 Memory Spaces Boot-Space P-Space $FFFF $FFFF $FFFF Not Accessible Not Accessible Not Accessible $1600 $15FF P-RAM $0200 $01FF Boot-ROM $0000 Serial Audio Interface (SAI) The SAI is used to deliver digital audio to the DSPs ...
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TDA7500A The features of the EMI are listed below. Data bus width fixed at 4 bits for DRAM and 8 bits for SRAM Data word length bits for DRAM Data word length ...
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Asynchronous Sample Rate Converter The ASRC, embedded in the TDA7500A, offers a fully digital stereo asynchronous sample rate conversion of digital audio sources to the TDA7500A's internal sample frequency. This solves the problem of mixing audio sources with different sample ...
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TDA7500A Codec The CODEC is composed of four AD mono converters, three DA stereo converters. The ADC can operate both in audio mode and in FM/AM mode. When in audio mode, it converts the audio bandwidth from 20 to 20KHz. ...
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Distortion Limiting Premium Equalization Soft mute TAPE Signal Processsing Dolby B Noise Reduction Automatic Music Search CD Signal Proceessing Dynamic Range Compression Audiophile Parametric Equalization Crossover Channel Delays Center Channel Imaging Output Audio Noise Reduction Other Voice compression/decompression for TIM ...
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TDA7500A Figure 20. lock Diagram of Car Amplifier Audio Sub-System. FRONT END Clock Scheme When TDA7500A is used in AD/FM mode the following scheme is choosen in order to avoid harmonics inside the FM band. Parts of the system are ...
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APPLICATION DIAGRAM The application diagram shown on the next page must be considered as one of the examples of a (limited) ap- plication of the chip. For the real application set-up the application notes are necessary. Figure 22. Application diagram. ...
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TDA7500A PACKAGE MARKING 38/40 ...
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DIM. MIN. TYP. MAX. MIN. A 1.60 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 B 0.17 0.22 0.27 0.007 C 0.09 0.20 0.003 D 16.00 D1 14.00 D3 12.00 e 0.50 E 16.00 E1 14.00 E3 12.00 ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...