E-TDA7590 STMicroelectronics, E-TDA7590 Datasheet
E-TDA7590
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E-TDA7590 Summary of contents
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... MP3 decoding Table 1. Device summary Order code E-TDA7590 E-TDA7590TR 1. In ECOPACK® package (see Section 9: Package information on page January 2009 Digital signal processing IC for speech and Description The TDA7590 is a high performances, fully programmable 24-bit, 120 MIPS. Digital signal ...
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... Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 Electrical characteristics for I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . bit DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 DSP peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1 Serial audio interface (SAI 7.2 Serial communication interface (SCI 7 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.4 Host interface (HI 7.5 ESSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.6 EOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.7 Timers and watchdog block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 ...
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... TDA7590 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Contents 3/42 ...
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... List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Thermal data Table 4. Key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 6. Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 7. General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4/42 TDA7590 ...
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... TDA7590 List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Pin connection (top view Figure 3. TQFP144 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 List of figures 5/42 ...
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... Block diagram 1 Block diagram Figure 1. Block diagram 2 Channel Codec ESSI SAI/CCT PLL Clock Oscillator PROM MOZART core EBUG Interface 120MIPs, 32 GPIOs 6/42 HOST i/f ESSI/12C SCI YRAM 68/64/56/48K x 24 XRAM 4/8/16/14K x 24 PRAM 16K x 24 Expansion Port TDA7590 Triple Timer FLEX RAM ...
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... TDA7590 2 Pin description 2.1 Pin connection Figure 2. Pin connection (top view) 143 141 139 137 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 SRD1 1 STD1 2 SC02 3 SC01 4 DE_N 5 NMI 6 7 SRD0 ...
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... SCAN enable. When active with TESTEN also active, controls the shifting of I the internal scan chains. Test enable. When active, puts the chip into test mode and muxes the XTI I clock to all flip-flops. When SCANEN is also active, the scan chain shifting is enabled. I Core ground. I Core power supply ...
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... Host address 8. Address line 8 in multiplexed mode otherwise address line 1 in non-multiplexed mode. Host address strobe. Address strobe for multiplexed bus or Address 0 for non multiplexed. Host 8-bit data line 7. Host data bus and/or address lines when in multiplexed mode. Pin description Description ...
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... Host 8-bit data line 6. Host data bus and/or address lines when in multiplexed mode. Host 8-bit data line 5. Host data bus and/or address lines when in multiplexed mode. Host 8-bit data line 4. Host data bus and/or address lines when in multiplexed mode. I Core power supply. ...
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... Address bus line 13. Port A external address bus. Address bus line 14. Port A external address bus. Address bus line 15. Port A external address bus. Address bus line 16. Port A external address bus. Address bus line 17. Port A external address bus. Address bus line 18. Port A external address bus. ...
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... Test data input. JTAG input pin for serial data input for debug interface. I Test clock. JTAG input pin for clocking debug interface. Test mode select. JTAG input pin for control of TAP Controller of debug I interface. Test data output. JTAG output pin for serial data out from debug interface. ...
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... Thermal resistance junction to pins th-j-pins Description Serial control 2.Transmitter frame sync only in asynchronous mode, transmitter and receiver frame sync in synchronous mode. Serial control 1. Receive frame sync in asynchronous mode, output from transmitter 2 or serial flag 1 in synchronous mode SDA. Serial data line. Parameter Pin description ...
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... Key parameters 3 Key parameters 3.1 Power consumption Power consumption depends on application running and DSP clock frequency. Supply current values are measured and guaranteed at testing level by adopting the benchmarking program reported in Appendix 1. Table 4. Key parameters Symbol General fosc Crystal frequency CORE_VDD Operating voltage ...
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... Total harmonic distortion to signal (THD)/S THD is defined as the ratio of the sum of only those components of the output signal which are harmonic of system input, after having removed the fundamental tone corresponding to the pure sine wave as input and the input signal.This measurement is done by using the ...
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... High level output voltage 1. TTL specifications only apply to the supply voltage range Vdd = 3.15V to 3.6V. 2. Takes into account 200mV voltage drop in both supply lines the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability. 16/42 ...
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... TDA7590 5 24 bit DSP core The DSP core is a general purpose 24-bit DSP. The main feature of the DSP core are listed below: ● 120 MHz operating frequency (120 MIPS) ● Fully pipelined bit parallel multiplier-accumulator ● Saturation/limiting logic ● 56-bit parallel barrel shifter ● ...
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... K x 24-bit RAM divided into 4 areas, program RAM(PRAM), X data RAM(XRAM), Y data RAM(YRAM) and flexible allocation RAM(FLEX) as follows: ● PRAM ● FLEX RAM. FLEX RAM is accessed through the expansion port by the DSP core. ● External access to the FLEX RAM is also supported. ● ...
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... The SAI is used to communicate between the CODEC and the DSPs. In addition, digital audio can be directly input for processing. There is only one SAI found on the chip that can be accessed by either the DSP or the DMA controller. The main features of this block are listed below: – ...
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... ESSI The ESSI peripheral enables serial-port communication between the DSP core and external devices including Codecs, DSP, microprocessors. The ESSI is capable of driving 12 programmable external pins which can be configured as GPIO ports C and D or ESSI pins. The key features of the ESSI are: ● ...
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... Sampling rates of 8 kHz to 48 kHz The analog interface is in the form of differential signals for each channel. The interface on the digital side has the form of an SAI interface and can interface directly to an SAI channel and then to the DSP core. DCLK can be supplied either by the internal PLL or by external, to allow synchronization with external anal digital sources ...
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... M_PDRE EQU M_OGDB EQU ;------------------------------------------------------------------------ ; EQUATES for Exception Processing ;------------------------------------------------------------------------ ; Register Addresses IPR_C EQU 22/42 CODEC + TIMER + HI gpios + ESSI + SCI 20 4 $FFFFC9 ; PS- Host port GPIO data Register $FFFFC8 ; PS- Host port GPIO direction Register $FFFFBF ; Port C Control Register $FFFFBE ; Port C Direction Register $FFFFBD ; Port C GPIO Data Register $FFFFAF ...
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... Timer0 Overflow $28 ; Timer1 Compare $2A ; Timer1 Overflow $2C ; Timer2 Compare $2E ; Timer2 Overflow $000050 ; SCI receive data $000052 ; SCI receive data with exception status $000054 ; SCI transmit data $000056 ; SCI idle line $000058 ; SCI timer 6 $000000 ; Reset address location $FFFFFF ; SAI Receive Control/Status Register $FFFFFE ...
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... DAC Right Gain Bit DAC Right Gain Bit Mute DAC - Active Hi, Reset Val = Power down DAC - Active Hi, Reset Val = Power down ADC - Active Hi, Reset Val = Asynchronoue Reset - Active Lo, Reset Val = 1 $FFFFD7 ; PLL Control/Status Register $FFFFD6 ; PLL Fractional Register $FFFFD5 ; PLL Clock Control Register 0 ...
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... DSP_XTI =0 -> Use VCO/DSPDF ; DSP_XTI =1 -> Use XTI 19 ; Selects between VCO and ext_dac_clk 20 ; Disables the external crystal when set $FFFFC9 ; PS- Host port GPIO data Register $FFFFC8 ; PS- Host port GPIO direction Register $FFFFBF ; Port C Control Register $FFFFBE ; Port C Direction Register $FFFFBD ; Port C GPIO Data Register $FFFFAF ...
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... GPIO0_DIR EQU GPIO1_DIR EQU GPIO2_DIR EQU GPIO3_DIR EQU GPIO4_DIR EQU GPIO5_DIR EQU GPIO6_DIR EQU GPIO7_DIR EQU GPIO8_DIR EQU ;;; Bit Definitions for GPIO Data Register GPIO0_DAT EQU GPIO1_DAT EQU GPIO2_DAT EQU GPIO3_DAT EQU GPIO4_DAT EQU GPIO5_DAT EQU GPIO6_DAT EQU GPIO7_DAT EQU GPIO8_DAT EQU ...
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... SSI1 Receive Data Register $FFFFA7 ; SSI1 Status Register $FFFFA6 ; SSI1 Control Register B $FFFFA5 ; SSI1 Control Register A $FFFFA4 ; SSI1 Transmit Slot Mask Register A $FFFFA3 ; SSI1 Transmit Slot Mask Register B $FFFFA2 ; SSI1 Receive Slot Mask Register A $FFFFA1 ; SSI1 Receive Slot Mask Register B $FFFF9F ...
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... EXP_AAR0 EQU EXP_AAR1 EQU EXP_AAR2 EQU EXP_AAR3 EQU EXT_RAM_STARTEQU ;------------------------------------------------------------------------ ; EQUATES for Extended Memory ;------------------------------------------------------------------------ EOC_ADR EQU ;******************************************************************************* ;***************************** Initialisation Values ;******************************************************************************* ;------------------------------------------------------------------------------- ; CODEC Intitialisation values ;------------------------------------------------------------------------------- ; --- INIT_CCR ----------------------------------------------------------------- ; settings fro the CODEC Control Register ; INIT_CODEC_CSR EQU ; ; ; ; ; ; ; ; ;------------------------------------------------------------------------------- ; SAI Intitialisation values ;------------------------------------------------------------------------------- ;--- INIT_RCS ------------------------------------------------------------------ ; settings for the Receiver Control/Status Register ; INIT_SAI_RCS EQU ; ; ...
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... PLL control register ; ;INIT_PLL_CSR EQU INIT_PLL_CSR EQU ; ; ; ; ; ; ; ; ; ; ;--- FRACT --------------------------------------------------------------------- ; settings for the Fractional N part of the PLL ; ;INIT_PLL_FCR EQU INIT_PLL_FCR EQU ; ;--- CLKCTL -------------------------------------------------------------------- 0 ------------------ RDR 0 ------------------- ROFCL 321098765432109876543210 %000000000001010101001001 ; $000549 - non incrociato 1 --- T0EN (0:Disbaled; 1:Enabled) 0 ---- T1EN (0:Disbaled; 1:Enabled) 0 ----- T2EN (0:Disbaled; 1:Enabled) 1 ------ TMME (1:Master mode; 0:Slave mode) 0 ------- reserved 10 -------- TWL[0:1] (00:16 ...
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... TOIE 0 -> $000000 $000000 $000000 $000002 $000004 $000008 $000000 $000000 mode0 / trm=1 / tce=1 / pce=1/ dir=out mode0 / trm=1 / tce=1 / pce=1/ dir=out mode0 / trm=1 / tce=1 / pce=1/ dir=out ; Timer Compare Flag ; Timer Overflow Flag ; unused ; Prescaler Clock Enable ; unused ; Data Output ; Data Input ; Direction ...
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... Synchronous SRAM; 01: SRAM; 10: DRAM; 11: Reserved) 0 ----- BAAP (0:AA1 active low; 1: AA1 active high) 0 ------ BPEN (0: P space disabled space enabled) 1 ------- BXEN (0: X data space disabled data space enabled) 0 -------- BYEN (0: Y data space disabled data space enabled) 0 --------- BAM (0: 8 LSB of address will appear on A0-A7; ...
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... Appendix 1 ; settings for the Bus Control Register ; INIT_BCR EQU ;INIT_BCR EQU ; ; ; ; ; ; ; ; ;******************************************************************************* ; definitions addded by Paul Cassidy for salieri testbench TRIGGER_TUBE EQU M_BCR EQU M_AAR0 EQU M_AAR1 EQU M_AAR2 EQU M_AAR3 EQU ;******************************************************************************* ;************************** Main Prog Starts Here ****************************** ;******************************************************************************* startp org p:$0 jmp start sci_int org p:SCI_REC ...
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... INT_TMR1_tof org p:Timer2_tcf jsr INT_TMR2_tcf org p:Timer2_tof jsr INT_TMR2_tof org x:0 states dsm ntaps org y:0 coef dc .1,.3,-.1,.2 org p:$100 start ; setup external memory for sync with testbench ;------------------------------------------------------------------------ ; Initialise Core ;------------------------------------------------------------------------ clr a clr b move #$0,r0 move #$fff,m0 ori #$3,mr ...
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... Initialise SAI ;------------------------------------------------------------------------ ; The receiver and transmitter control/status register are configured the same for simplicity only. ; Master mode , 24-bit word-size , MSB first , Low word clock = left word , Neg bit-clk polarity , ; Non i2s format , (For 32-bit words) First bit Interrupts enabled. init_sai movep ...
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... Disable Timer2 ; Timer0 enable at mode 0 + reload ; Initial value of the timer counter ; Initial value of the timer counter ; Number of CLK/2 cycles until a trigger is generated ; Timer1 enable at mode 0 + reload ; Initial value of the timer counter ; Initial value of the timer counter ; Number of CLK/2 cycles until a trigger is generated ...
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... DSP interrupt priority level Sets the Interrupt Mask bits in the [00] (No exceptions masked) ; Enable Timer0 ; Enable Timer1 ; Enable Timer2 ; start SCI transmit ; start SCI transmit x:(r3)+,x0 y:(r4)+,y0 ; generates variations on mean value of DAC ...
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... Load LEFT transmit data register for channel 0 ; Load RIGHT transmit data register for channel 0 ; The receiver data ready flag is cleared as soon ; as the last move is performed ; Move Channel 0 received LEFT data to x-memory. ; Move channel 0 received RIGHT data to y-memory. ...
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... Comp_0 rti 38/42 ; toggle pin12 Fout=(XTI/2)/((TPLR+1)*(TCPR+1)*2) ; toggle TIO0 Fout=(XTI/2)/((TPLR+1)*(TCPR+1)*2) ; toggle pin4 Fout=Fin/((TPLR+1)*(TCPR+1)*2) ; toggle TIO1 Fout=(XTI/2)/((TPLR+1)*(TCPR+1)*2) ; toggle pin3 Fout=Fin/((TPLR+1)*(TCPR+1)*2) ; toggle TIO2 Fout=(XTI/2)/((TPLR+1)*(TCPR+1)*2) TDA7590 ...
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... INT_SCIR move x:SRXL_ADR,x0 movep #$3f02,x:SCR_ADR ; move x0,x:(r1)+ ; move x0,x:$C00000 rti INT_SCIT ; movep x0,x:STXA_ADR movep #$000041,x:STXA_ADR ; movep #$000061,x:STXA_ADR L3 jclr #0,x:<<SSR_ADR,L3 movep #$12f02,x:SCR_ADR rti INT_SCIE jclr #FRAMING,x:SSR_ADR,NO_FRA L2 jclr #0,x:<<SSR_ADR,L2 movep #$21,x:STXA_ADR NO_FRA nop move x:SRXL_ADR,x0 rti Appendix 1 39/42 ...
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... Package information 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Figure 3. TQFP144 mechanical data and package dimensions DIM ...
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... TDA7590 10 Revision history Table 8. Document revision history Date 11-Apr-2006 26-Jan-2009 Revision 1 Initial release. Document status promoted from preliminary data to datasheet. 2 Updated Section 9: Package information on page Revision history Changes 40. 41/42 ...
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