STA30613TR STMicroelectronics, STA30613TR Datasheet

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MULTICHANNEL DIGITAL AUDIO PROCESSOR WITH DDX™ 6 DDX TM Channels Capability (24 bit) From 32kHz to 192kHz Input Sample Rates Supported Volume Control from 0 to -127 dB (0.5 dB steps) Variable Digital Gain from 0 to 24dB (0.5dB steps) ...

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STA306 BLOCK DIAGRAM LRCKI LRCKI BICKI BICKI SERIAL SERIAL DATA DATA SDI12 SDI12 IN IN SDI34 SDI34 SDI56 SDI56 CHANNEL CHANNEL MAPPING MAPPING SYSTEM TIMING SYSTEM TIMING PLLB PLLB PLL PLL XTI XTI CKOUT CKOUT Figure 1. Signal Flow Diagram ...

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IN CONNECTION (Top view) MVO TEST_MODE VDD3 GND VDD N.C. SDI_56 SDI_34 SDI_12 LRCKI BICKI VDD3 GND VDD RESET PLLB PIN FUNCTION PIN NAME 1 MVO 3, 12, 24, 28, VDD3 35, 44, 52 13, 27, GND ...

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STA306 PIN FUNCTION (continued) PIN NAME 20 XTI 21 FILTER_PLL 22 VDDA 23 GNDA 25 CKOUT 33 OUT6_B 34 OUT6_A 38 OUT5_B 39 OUT5_A 40 OUT4_B 41 OUT4_A 42 OUT3_B 43 OUT3_A 47 OUT2_B 48 OUT2_A 49 OUT1_B 50 OUT1_A ...

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ABSOLUTE MAXIMUM RATINGS Symbol V 3.3V I/O Power Supply DD_3.3 V 2.5V Logic Power Supply DD_2.5 V Voltage on input pins i V Voltage on output pins o T Storage Temperature stg T Ambient Operating Temperature amb THERMAL DATA Symbol ...

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STA306 ELECTRICAL CHARACTERISTCS (V wise specified) GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter I Low Level Input no pull- High Level Input no pull-down ih I Tristate output leakage without OZ pullup/down V Electrostatic Protection esd Note 1: The ...

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PIN DESCRIPTION 1.1 MVO: Master Volume Override This pin enables the user to bypass the Volume Control on all channels. When MVO is pulled High, the Master Volume Register is set to 00h, which corresponds to its Full Scale ...

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STA306 2.1 COMMUNICATION PROTOCOL 2.1.1 Data Transition or change Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition. ...

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Write Mode Sequence BYTE DEV-ADDR WRITE START MULTIBYTE DEV-ADDR WRITE START Read Mode Sequence ACK CURRENT DEV-ADDR ADDRESS READ START RW ACK RANDOM DEV-ADDR ADDRESS READ START RW RW= ACK HIGH SEQUENTIAL DEV-ADDR CURRENT READ START ACK SEQUENTIAL DEV-ADDR RANDOM ...

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STA306 10h C8Vol C8V7 11h C12im 12h C34im 13h C56im 14h C78im 15h C1234ls C4LS1 16h C5678ls C8LS1 17h L1ar L1R3 18h L1atrt L1AT3 19h L2ar L2R3 1Ah L2atrt L2AT3 1Bh Tone TTC3 1Ch Cfaddr CFA7 1Dh B2cf1 C1B23 1Eh ...

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CONFIGURATION REGISTER A (ADDRESS 00H) BIT D7 D6 NAME MPC HPE RST 1 0 3.0.1 Master Clock Select BIT R/W RST R/W 0 The STA306 will support sample rates of 32kHz, 44.1kHz, ...

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STA306 3.0.3 Bass Management Enable BIT R/W RST NAME 5 R/W 0 BME Channel 6 of the STA306 features a bass management mode that enables redirection of information in all other channels to this channel and which can then be ...

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Serial Audio Input Interface Format BIT R/W RST R/W 0 The STA306 features a configurable digital serial audio interface. The settings of the SAIx bits determine how the input to this interface is ...

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STA306 3.1.3 Serial Audio Input Interface First Bit BIT R/W RST NAME 5 R/W 0 SAIFB 3.1.4 Zero-Crossing Volume Enable BIT R/W RST NAME 6 R/W 1 ZCE The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on ...

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High-Pass Filter Bypass BIT R/W RST 7 R/W 0 The STA306 features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a DDX amplifier. ...

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STA306 3.3.4 Biquad Coefficient Link BIT R/W RST NAME 7 R/W 0 BQL For ease of use, all channels can use the biquad coefficients loaded into the Channel 1 Coefficient RAM space by setting the BQL bit to 1. Then ...

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Table 4. Interface format as a function of SAO bits. SAO(2..0) Interface Format 000 001 Left-Justified Data 010 Right-Justified 16-bit Data 011 Right-Justified 18-bit Data 100 Right-Justified 20-bit Data 101 Right-Justified 24-bit Data BIT R/W RST 6 ...

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STA306 3.7 Master Volume Register (address 07h) BIT D7 D6 NAME MV7 MV6 RST 1 1 3.8 Channels 1,2,3,4,5,6 Mute (address 08h) BIT D7 D6 NAME C8M C7M RST 0 0 3.9 Channel 1 Volume (address 09h) BIT D7 D6 ...

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Channel 6 Volume (address 0Eh) BIT D7 D6 NAME C6V7 C6V6 RST 0 0 The Volume structure of the STA306 consists of individual volume registers for each channel and a master vol- ume register that provides an offset to ...

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STA306 Table 5. Master Volume Offset as a function of MV(7..0). MV(7..0) 00000000(00h) 00000001(01h) 00000010(02h) … 01001100(4Ch) … 11111110(FEh) 11111111(FFh) Channel Volume as a function of CxV(7..0) CxV(7..0) 00000000(00h) 00000001(01h) 00000010(02h) … 00101111(2Fh) 00110000(30h) 00110001(31h) … 11111110(FEh) 11111111(FFh) 3.15 Channel ...

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Each channel received via I2S can be mapped to any internal processing channel via the Channel Input Map- ping registers. This allows for flexibility in processing, simplifies output stage designs, and enables the ability to perform crossovers. The default settings ...

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STA306 3.18 Channel Limiter Select Channels 1,2,3,4 (address 15h) BIT D7 D6 NAME C4LS1 C4LS0 RST 0 0 3.19 Channel Limiter Select Channels 5,6 (address 16h) BIT D7 D6 NAME C8LS1 C8LS0 RST 0 0 3.20 Limiter 1 Attack/Release Rate ...

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Basic Limiter and Volume Flow Diagram. Gain/Volume Input Gain A limiter is basically a variable gain device, where the amount of gain applied depends on the input signal level. As the name implies, compression limits the dynamic range of the ...

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STA306 Table 8. Limiter Attack Rate as a function of LxA bits. LxA(3..0) 0001 0010 0011 LxA(3..0) 0000 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 note: Shaded areas are Default Settings Table 9. Limiter Release Rate and ...

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Table 10. Limiter Attack Threshold as a function of LxAT bits. LxAT(3..0) AC(dB relative to FS) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 11. Limiter Release Threshold as a function ...

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STA306 3.24 Bass and Treble Tone Control(address 1Bh) BIT D7 D6 NAME TTC3 TTC2 RST 0 1 The STA306 contains bass and treble tone control adjustments. These are selectable from +12dB to -12dB of boost or cut. These are 1st ...

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Coefficient b2 Data Register Bits 7..0 (address 1Fh) BIT D7 D6 NAME C1B7 C1B6 RST 0 0 3.29 Coefficient b0 Data Register Bits 23..16 (address 20h) BIT D7 D6 NAME C2B23 C2B22 RST 0 0 3.30 Coefficient b0 Data ...

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STA306 3.36 Coefficient a1 Data Register Bits 15..8 (address 27h) BIT D7 D6 NAME C4B15 C4B14 RST 0 0 3.37 Coefficient a1 Data Register Bits 7..0 (address 28h) BIT D7 D6 NAME C4B7 C4B6 RST 0 0 3.38 Coefficient b1 ...

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Writing a single coefficient to RAM – write 8-bit address to I2C register 1Ch – write top 8-bits of coefficient in I2C address 1Dh – write middle 8-bits of coefficient in I2C address 1Eh – write bottom 8-bits of coefficient ...

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STA306 single 28-bit signed multiply, with 800000h = -1 and 7FFFFFh = 0.9999998808. These values are labeled CxPS, with x representing the channel. The biquads use this equation: Y[n] = 2(b0/2)X[n] + 2(b1/2)X[n-1] + b2X[n-2] - 2(a1/2)Y[n-1] - a2Y[n-2] = ...

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Channel 1 - Biquad 5 25 19h Channel 2 - Biquad 1 26 1Ah … … … 45 2Dh Distortion Compensation … … … 49 31h Channel 2 - Biquad 5 50 32h Channel 3 - Biquad 1 ...

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STA306 mm DIM. MIN. TYP. MAX. MIN. A 1.60 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 B 0.17 0.22 0.27 0.0066 0.0086 0.0086 C 0.09 0.0035 D 11.80 12.00 12.20 0.464 D1 9.80 10.00 10.20 0.386 D3 7.50 ...

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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...