TDA7460ND STMicroelectronics, TDA7460ND Datasheet - Page 29

• Manufacturer Part Number: TDA7460ND
• Description: IC PROCESSOR CAR RAD SGNL SO-20
• Manufacturer: STMicroelectronics
• Type: Car Signal Processorr

Specifications of TDA7460ND

• Applications: Automotive Systems
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TDA7460ND
5.5.5
5.5.6
5.5.7
5.5.8
PLL and pilot tone detector
The PLL has the task to lock on the 19kHz pilotone during a stereo transmission to allow a
correct demodulation. The included detector enables the demodulation if the pilot tone
reaches the selected pilottone threshold VPTHST. Two different thresholds are available.
The detector output (signal STEREO, see
reading the status byte of the TDA7460ND via I
Fieldstrength control
The fieldstrength input is used to control the high cut and the stereo blend function. In
addition the signal can be also used to control the noise blanker thresholds.
Level input and gain
To suppress undesired high frequency modulation on the high cut and stereo blend function
the LEVEL signal is lowpass filtered firstly. The filter is a combination of a 1
lowpass at 53 kHz (working as anti-aliasing filter) and a 1st-order switched capacitor
lowpass at 2.2 kHz. The second stage is a programmable gain stage to adapt the LEVEL
signal internally to different IF.
The gain is widely programmable in 16 steps from 0 dB to 10 dB (step = 0.67 dB). These 4
bits are located together with the roll-off bits in the "Stereo decoder Adjustment" byte to
simplify a possible adaptation during the production of the carradio.
Figure 23. Internal stereo blend characteristics
Stereo blend control
The stereo blend control block converts the internal LEVEL voltage (LEVEL INTERN) into
an demodulator compatible analog signal which is used to control the channel separation
between 0dB and the maximum separation. Internally this control range has a fixed upper
limit which is the internal reference voltage REF5V. The lower limit can be programmed to
be 33%, 42%, 50% or 58% of REF5V (see
To adjust the external LEVEL voltage to the internal range two values must be defined: the
LEVEL gain L
reached (VST) the LEVEL gain LG has to be defined. The following equation can be used to
estimate the gain:
G
and VSBL. To adjust the voltage where the full channel separation is
-------------------------------------------------------------------------
Field strenght voltage [STER
Figure 1: Block
Figure
REF5V
2
C bus.
24.).
diagram) can be checked by
Stereo decoder part
st
order RC
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