E-TDA7333013TR STMicroelectronics, E-TDA7333013TR Datasheet
E-TDA7333013TR
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E-TDA7333013TR Summary of contents
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... Table 1. Device summary Operating temp. range, °C (1) Order code E-TDA7333 E-TDA7333013TR 1. Devices in ECOPACK® package (see June 2008 Description The TDA7333 circuit is a RDS/RDBS signal processor, intended for recovering the inaudible RDS/RBDS informations which are transmitted on most FM radio broadcasting stations. ...
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... Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Quick reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Sigma delta converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 Sinc4/16 decimation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 ...
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... TDA7333 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 6. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 7. External pins alternate functions Table 8. Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 9. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 List of tables 3/26 ...
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... List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Pin connection (top view Figure 3. Transfer function Figure 4. Magnitude response of sinc. 4/16 filter in RDS band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Transfer function of RDS bandpass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Phase response of the RDS bandpass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7. Demodulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 8. Group and block synchronization block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 9 ...
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... TDA7333 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram REF1 MPX 16 Cmpx SCL_CLK 11 SDA_DATAIN 12 SA_DATAOUT 13 CSN 14 1.2 Pin description Figure 2. Pin connection (top view) Cxti Cref Cref Cref 16pF REF2 REF3 XTI OSCILLATOR SIGMA DELTA SINC4 converter filter ...
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... Clock signal for I C and SPI modes 2 Data line mode, data input in SPI mode 2 C mode, data output in SPI mode 2 Chip select ( mode, 0=SPI mode) Interrupt output (active low), prog. at buff.not empty, buff. full, block A,B,D ,TA, TA EON Multiplex input signal TDA7333 ...
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... General interface electrical characteristics Symbol Parameter I Low level input current il I High level input current ih I Tri-state output leakage oz = 8.55 MHz) osc Parameter 2 C mode Test conditions 5 V tolerant inputs 5 V tolerant output buffers in tri-state Test conditions 5 Electrical specifications Min. Typ. ...
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... Low level threshold input V ilhyst falling High level threshold input V ihhyst rising V Schmitt trigger hysteresis hst Digital outputs (pin 12,13,15) are open drains V High level output voltage oh V Low level output voltage ol Analog inputs (pin 16) V Input range of MPX signal MPX ...
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... TDA7333 Table 6. Electrical characteristics (continued -40 to +85 °C, V amb V and V must not differ more than 0.15 V DDD DDA Symbol Parameter Sigma delta modulator F Sample rate s OVR Oversampling ratio Relative total harmonic dist. THD+N plus noise Sinc4/16 decimation filter f Decimated sample rate s A57 ...
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... It is implemented by cascading 4 integrators operating at full sampling rate (XTI/2) followed by 4 differentiates operating at the reduced sampling rate (XTI/2/16). Also wrap around logic is allowed and the internal overflow will not affect the output signal as long as a minimum required bit width is maintained. The transfer function of this Sinc4/16 filter is: ...
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... TDA7333 and its frequency response is: with Figure 3. Transfer function 100 0 Figure 4. Magnitude response of sinc. 4/16 filter in RDS band 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.4 ⎛ Mω ⎛ -------- - sin ⎝ ⎜ jω ⎜ ---- - ----------------------- = ω ⎜ M ⎛ ⎞ sin --- - ⎝ ⎝ ⎠ ω ...
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... The output sample of the bandpass filter is picked up from a linear interpolator with sinc2 characteristics. The interpolation factor is 32. A zero cross detection is simply formed by taking the sign bit of the interpolated signal. This signal which contains only phase informations is processed by the RDS Demodulator. 12/26 Transfer Function of RDS Filter 4 ...
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... The sign of both channels are used as input for the ARI indicator and for the 57 kHz PLL. A fast ARI indicator determines the presence of an ARI carrier ARI carrier is present, the 57 kHz PLL is operating as a normal PLL, else it is operating as a Costas loop ...
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... Functional description bits marked as bad by the quality bit are allowed to be corrected in the group and block synchronization module. Thus the error correction is directly influenced by this setup. The time constant of the 57 kHz PLL and the 1187.5 Hz PLL may be influenced by software (see Chapter 3 ...
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... CSN is high, the interface operates ● if the pin CSN is asserted low, the interface operates as a SPI bus. In both modes, the device is a slave, i.e the clock pin SCL_CLK is only an input for the chip. Depending on the transfer mode, external pins have alternate functions as following: Table 7. ...
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... E is detected.This indicates a paging block which is defined in the RBDS specification used in the united states of America ordinary RDS block c· detected valid syndrome was found. bit 0 of block counter (2) bit 1 of block counter (2) bit 0 of quality counter (3) ...
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... Specification of the radio data system EN50067 of CENELEC, ANNEX B). When bits 4...0 of the syndrome register are all zero a possible error burst is stored in this bits. With the help of the correction pattern(bits 9..5 of the syndrome register), the type of error can be measured in or- der to classify the reliability of the correction ...
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... Note: Sinc4reg and testreg are reserved registers dedicated to testing and evaluation. 18/26 bit 5 bit 4 bit 3 bit 2 bit 1 bit ...
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... The interface is capable of operating in fast mode (up to 400kbits/s) but also at lower rates (<100kbits/s). Data transfers follow the format shown in address is sent. The address is 7 bits long followed by an eighth bit which is a data direction bit (R/_W). A ’zero’ indicates a transmission (WRITE), a ’one’ indicates a request for data (READ). ...
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... Eight bytes can be read at a time (please refer to The master has always the possibility to read less than eight registers by not sending the acknowledge bit and then generating a stop condition after having read the needed amount of registers. ...
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... The chip select input signals the begin and end of the data transfer. If the data transfer starts, at each bit clock one bit is clocked out via the serial data output and one bit is clocked in via the serial data input. When chip enable signals the begin of the data transfer the internal 64 bits shift register is updated with the current registers content of the V324 ...
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... Figure 24. Write rds_int registers in SPI mode, reading 1 register CSN CLK DATAIN DATAOUT The content of the rds registers is clocked out on DATAOUT pin in the following order: rds_int[7:0], rds_qu[7:0], rds_corrp[7:0], rds_bd_l[7:0], rds_bd_h[7:0], rds_ctrl[7:0], sinc4reg[7:0], testreg[7:0] For the meaning of the single bits please refer to the Note: After 40 bit clocks the whole RDS data and flags are clocked out ...
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... The output pin INTN acts as an interrupt pin. The source of interrupt is programmable through the register rds_int (see the bit rds_int[0] (i.e this interrupt pin is active low). With the help of this pin an interrupt driven request of the rds data is possible (the external processor only starts the transfer if an interrupt is active) ...
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... In order to meet environmental requirements, ST (also) offers these devices in ECOPACK® packages. ECOPACK® packages are lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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... TDA7333 6 Revision history Table 9. Document revision history Date 25-Jun-2008 Revision 1 Initial release. Revision history Changes 25/26 ...
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