LPC1112FDH28 NXP Semiconductors, LPC1112FDH28 Datasheet
LPC1112FDH28
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LPC1112FDH28 Summary of contents
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LPC1110/11/12/13/14/15 32-bit ARM Cortex-M0 microcontroller flash and 8 kB SRAM Rev. 7 — 1 March 2012 1. General description The LPC1110/11/12/13/14/15 are a ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering ...
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... NXP Semiconductors GPIO pins can be used as edge and level sensitive interrupt sources. High-current output driver (20 mA) on one pin. High-current sink drivers (20 mA) on two I LPC1112FDH20/102). Four general purpose counter/timers with up to eight capture inputs and match outputs. ...
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... Ordering information (LPC1100 and LPC1100L series) Type number Package Name SO20, TSSOP20, TSSOP28, and DIP28 packages LPC1110FD20 SO20 LPC1111FDH20/002 TSSOP20 LPC1112FD20/102 SO20 LPC1112FDH20/102 TSSOP20 LPC1112FDH28/102 TSSOP28 LPC1114FDH28/102 TSSOP28 LPC1114FN28/102 DIP28 HVQFN33 and LQFP48 packages LPC1111FHN33/101 HVQFN33 LPC1111FHN33/102 HVQFN33 LPC1111FHN33/201 HVQFN33 LPC1111FHN33/202 ...
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... NXP Semiconductors Table 1. Ordering information (LPC1100 and LPC1100L series) Type number Package Name LPC1113FHN33/302 HVQFN33 LPC1114FHN33/201 HVQFN33 LPC1114FHN33/202 HVQFN33 LPC1114FHN33/301 HVQFN33 LPC1114FHN33/302 HVQFN33 LPC1114FHI33/302 HVQFN33 LPC1113FBD48/301 LQFP48 LPC1113FBD48/302 LQFP48 LPC1114FBD48/301 LQFP48 LPC1114FBD48/302 LQFP48 Table 2. Ordering information (LPC1100XL series) Type number Package ...
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... Series LPC1110 LPC1110FD20 LPC1100L LPC1111 LPC1111FDH20/002 LPC1100L LPC1111FHN33/101 LPC1100 LPC1111FHN33/102 LPC1100L LPC1111FHN33/201 LPC1100 LPC1111FHN33/202 LPC1100L LPC1112 LPC1112FD20/102 LPC1100L LPC1112FDH20/102 LPC1100L LPC1112FDH28/102 LPC1100L LPC1112FHN33/101 LPC1100 LPC1112FHN33/102 LPC1100L LPC1112FHN33/201 LPC1100 LPC1112FHN33/202 LPC1100L LPC1112FHI33/202 LPC1100L LPC1113 LPC1113FHN33/201 LPC1100 LPC1113FHN33/202 LPC1100L LPC1113FHN33/301 LPC1100 LPC1113FHN33/302 LPC1100L ...
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... NXP Semiconductors Table 3. Ordering options(LPC1100 and LPC1100L series) Type number Series LPC1114FDH28/102 LPC1100L LPC1114FN28/102 LPC1100L LPC1114FHN33/201 LPC1100 LPC1114FHN33/202 LPC1100L LPC1114FHN33/301 LPC1100 LPC1114FHN33/302 LPC1100L LPC1114FHI33/302 LPC1100L LPC1114FBD48/301 LPC1100 LPC1114FBD48/302 LPC1100L Table 4. Ordering options (LPC1100XL series) Type number Series LPC1111 LPC1111FHN33/103 LPC1100XL 8 kB ...
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... NXP Semiconductors 5. Block diagram LPC1110/11/12/13/14 HIGH-SPEED GPIO ports GPIO PIO0/1/2/3 RXD TXD (5) DTR, DSR, CTS , (5) DCD, RI, RTS (3) CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 (3) CT32B0_CAP0 (3) CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 (3) CT32B1_CAP0 (3) CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 (3) CT16B0_CAP0 (3) CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 (3) CT16B1_CAP0 (1) LQFP48 packages only. (2) Not on LPC1112FDH20/102. ...
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... NXP Semiconductors LPC1111/12/13/14/15XL HIGH-SPEED GPIO ports GPIO PIO0/1/2/3 RXD TXD (1) DTR, DSR , CTS, (1) (1) DCD , RI , RTS CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 CT32B0_CAP[1:0] CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 CT32B1_CAP[1:0] CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP[1:0] CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 CT16B1_CAP[1:0] (1) LQFP48 only. Fig 2. LPC1100XL series block diagram LPC111X ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Table 5. Part LPC1110FD20 LPC1111FDH20/002 LPC1112FD20/102 LPC1112FDH20/102 LPC1112FDH28/102 LPC1114FDH28/102 LPC1114FN28/102 LPC1111FHN33/101 LPC1111FHN33/102 LPC1111FHN33/103 LPC1111FHN33/201 LPC1111FHN33/202 LPC1111FHN33/203 LPC1112FHN33/101 LPC1112FHN33/102 LPC1112FHN33/103 LPC1112FHN33/201 LPC1112FHN33/202 LPC1112FHN33/203 LPC1112FHI33/202 LPC1112FHI33/203 LPC1113FHN33/201 LPC1113FHN33/202 LPC1113FHN33/203 LPC1113FHN33/301 LPC1113FHN33/302 LPC1113FHN33/303 LPC1114FHN33/201 LPC1114FHN33/202 LPC1114FHN33/203 LPC1114FHN33/301 LPC1114FHN33/302 LPC1114FHN33/303 LPC1114FHN33/333 ...
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... NXP Semiconductors Table 5. Part LPC1113FBD48/302 LPC1113FBD48/303 LPC1114FBD48/301 LPC1114FBD48/302 LPC1114FBD48/303 LPC1114FBD48/323 LPC1114FBD48/333 LPC1115FBD48/303 PIO2_6 PIO2_0/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 V XTALIN XTALOUT V PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 PIO2_7 PIO2_8 Fig 3. LPC1100 and LPC1100L series pin configuration LQFP48 package LPC111X Product data sheet Pin description overview Pin description table ...
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... NXP Semiconductors PIO2_6/CT32B0_MAT1 PIO2_0/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 V XTALIN XTALOUT V PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 PIO2_7/CT32B0_MAT2/RXD PIO2_8/CT32B0_MAT3/TXD Fig 4. LPC1100XL series pin configuration LQFP48 package LPC111X Product data sheet LPC1113FBD48/303 6 LPC1114FBD48/303 LPC1114FBD48/323 7 LPC1114FBD48/333 8 DD LPC1115FBD48/303 All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 Fig 5. LPC1100 and LPC1100L series pin configuration HVQFN33 7x7 and 5x5 packages LPC111X Product data sheet terminal 1 index area XTALIN 4 XTALOUT Transparent top view All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 PIO1_8/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 Fig 6. LPC1100XL series pin configuration HVQFN33 PIO0_8/MISO0/CT16B0_MAT0 PIO0_9/MOSI0/CT16B0_MAT1 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 R/PIO0_11/AD0/CT32B0_MAT3 R/PIO1_0/AD1/CT32B1_CAP0 R/PIO1_1/AD2/CT32B1_MAT0 R/PIO1_2/AD3/CT32B1_MAT1 SWDIO/PIO1_3/AD4/CT32B1_MAT2 Fig 7. LPC1100L series pin configuration SO20 package LPC111X Product data sheet terminal 1 index area XTALIN 4 5 XTALOUT ...
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... V DDA LPC1112FDH20/102 6 V SSA 002aag597 PIO0_5/SDA PIO0_6/SCK0 6 LPC1112FDH28/102 V 7 DDA LPC1114FDH28/102 V 8 SSA 002aag598 All information provided in this document is subject to legal disclaimers. Rev. 7 — 1 March 2012 32-bit ARM Cortex-M0 microcontroller 20 PIO0_4/SCL 19 PIO0_2/SSEL0/CT16B0_CAP0 ...
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... NXP Semiconductors PIO0_8/MISO0/CT16B0_MAT0 PIO0_9/MOSI0/CT16B0_MAT1 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 R/PIO0_11/AD0/CT32B0_MAT3 R/PIO1_0/AD1/CT32B1_CAP0 R/PIO1_1/AD2/CT32B1_MAT0 R/PIO1_2/AD3/CT32B1_MAT1 SWDIO/PIO1_3/AD4/CT32B1_MAT2 PIO1_4/AD5/CT32B1_MAT3/WAKEUP PIO1_5/RTS/CT32B0_CAP0 Fig 11. LPC1100L series pin configuration DIP28 package LPC111X Product data sheet LPC1110/11/12/13/14/ PIO0_5/SDA 5 6 PIO0_6/SCK0 7 V DDA LPC1114FN28 SSA 102 002aag599 All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 6.2 Pin description Table 6. LPC1100L series: LPC1110/11/12 pin description table (SO20 and TSSOP20 package with I Symbol PIO0_0 to PIO0_11 [2] RESET/PIO0_0 17 [3] PIO0_1/CLKOUT/ 18 CT32B0_MAT2 [3] PIO0_2/SSEL0/ 19 CT16B0_CAP0 [4] PIO0_4/SCL 20 [4] PIO0_5/SDA 5 [3] PIO0_6/SCK0 6 [3] PIO0_8/MISO0/ 1 CT16B0_MAT0 [3] PIO0_9/MOSI0/ 2 CT16B0_MAT1 [3] SWCLK/PIO0_10/ 3 SCK0/ CT16B0_MAT2 LPC111X Product data sheet ...
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... NXP Semiconductors Table 6. LPC1100L series: LPC1110/11/12 pin description table (SO20 and TSSOP20 package with I Symbol [5] R/PIO0_11/ 4 AD0/CT32B0_MAT3 PIO1_0 to PIO1_7 [5] R/PIO1_0/ 7 AD1/CT32B1_CAP0 [5] R/PIO1_1/ 8 AD2/CT32B1_MAT0 [5] R/PIO1_2/ 9 AD3/CT32B1_MAT1 [5] SWDIO/PIO1_3/ 10 AD4/CT32B1_MAT2 [3] PIO1_6/RXD/ 11 CT32B0_MAT0 [3] PIO1_7/TXD/ 12 CT32B0_MAT1 [6] XTALIN 14 [6] XTALOUT [1] Pin state at reset for default function Input Output internal pull-up enabled (pins pulled up to full V no pull-up/down enabled ...
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... NXP Semiconductors [2] See Figure 46 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. [ tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see ...
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... NXP Semiconductors Table 7. LPC1100L series: LPC1112 pin description table (TSSOP20 with V Symbol [4] R/PIO0_11/ 4 AD0/CT32B0_MAT3 PIO1_0 to PIO1_7 [4] R/PIO1_0/ 7 AD1/CT32B1_CAP0 [4] R/PIO1_1/ 8 AD2/CT32B1_MAT0 [4] R/PIO1_2/ 9 AD3/CT32B1_MAT1 [4] SWDIO/PIO1_3/ 10 AD4/CT32B1_MAT2 [3] PIO1_6/RXD/ 11 CT32B0_MAT0 [3] PIO1_7/TXD/ 12 CT32B0_MAT1 DDA [5] XTALIN 14 LPC111X Product data sheet Start Type Reset Description logic ...
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... NXP Semiconductors Table 7. LPC1100L series: LPC1112 pin description table (TSSOP20 with V Symbol [5] XTALOUT SSA [1] Pin state at reset for default function Input Output internal pull-up enabled (pins pulled up to full V no pull-up/down enabled. [2] See Figure 46 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode ...
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... NXP Semiconductors Table 8. LPC1100L series: LPC1112/14 pin description table (TSSOP28 and DIP28 packages) Symbol [4] PIO0_5/SDA 5 [3] PIO0_6/SCK0 6 [3] PIO0_7/CTS 28 [3] PIO0_8/MISO0/ 1 CT16B0_MAT0 [3] PIO0_9/MOSI0/ 2 CT16B0_MAT1 [3] SWCLK/PIO0_10/ 3 SCK0/ CT16B0_MAT2 [5] R/PIO0_11/ 4 AD0/CT32B0_MAT3 PIO1_0 to PIO1_9 [5] R/PIO1_0/ 9 AD1/CT32B1_CAP0 [5] R/PIO1_1/ 10 AD2/CT32B1_MAT0 LPC111X Product data sheet Start Type Reset ...
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... NXP Semiconductors Table 8. LPC1100L series: LPC1112/14 pin description table (TSSOP28 and DIP28 packages) Symbol [5] R/PIO1_2/ 11 AD3/CT32B1_MAT1 [5] SWDIO/PIO1_3/ 12 AD4/CT32B1_MAT2 [5] PIO1_4/AD5/ 13 CT32B1_MAT3/ WAKEUP [3] PIO1_5/RTS/ 14 CT32B0_CAP0 [3] PIO1_6/RXD/ 15 CT32B0_MAT0 [3] PIO1_7/TXD/ 16 CT32B0_MAT1 [3] PIO1_8/ 17 CT16B1_CAP0 [3] PIO1_9/ 18 CT16B1_MAT0 DDA [6] XTALIN 20 [6] XTALOUT SSA ...
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... NXP Semiconductors [1] Pin state at reset for default function Input Output internal pull-up enabled (pins pulled up to full V no pull-up/down enabled. [2] See Figure 46 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode ...
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... NXP Semiconductors Table 9. LPC1100 and LPC1100L series: LPC1113/14 pin description table (LQFP48 package) Symbol Pin Start logic input [3] PIO0_8/MISO0/ 27 yes CT16B0_MAT0 [3] PIO0_9/MOSI0/ 28 yes CT16B0_MAT1 [3] SWCLK/PIO0_10/ 29 yes SCK0/ CT16B0_MAT2 [5] R/PIO0_11/ 32 yes AD0/CT32B0_MAT3 PIO1_0 to PIO1_11 [5] R/PIO1_0/ 33 yes AD1/CT32B1_CAP0 [5] R/PIO1_1 AD2/CT32B1_MAT0 [5] R/PIO1_2 ...
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... NXP Semiconductors Table 9. LPC1100 and LPC1100L series: LPC1113/14 pin description table (LQFP48 package) Symbol Pin Start logic input [5] PIO1_4/AD5 CT32B1_MAT3/ WAKEUP [3] PIO1_5/RTS CT32B0_CAP0 [3] no PIO1_6/RXD/ 46 CT32B0_MAT0 [3] PIO1_7/TXD CT32B0_MAT1 [3] no PIO1_8/ 9 CT16B1_CAP0 [3] no PIO1_9/ 17 CT16B1_MAT0 [5] no PIO1_10/AD6/ 30 CT16B1_MAT1 [5] PIO1_11/AD7 ...
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... NXP Semiconductors Table 9. LPC1100 and LPC1100L series: LPC1113/14 pin description table (LQFP48 package) Symbol Pin Start logic input [3] PIO2_3/RI/MOSI1 38 no [3] PIO2_4 19 no [3] PIO2_5 20 no [3] PIO2_6 1 no [3] PIO2_7 11 no [3] PIO2_8 12 no [3] PIO2_9 24 no [3] PIO2_10 25 no [3] PIO2_11/SCK0 31 no PIO3_0 to PIO3_5 [3] PIO3_0/DTR 36 no ...
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... NXP Semiconductors [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. Table 10. LPC1100 and LPC1100L series: LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin ...
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... NXP Semiconductors Table 10. LPC1100 and LPC1100L series: LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin Start logic input [5] R/PIO0_11/AD0/ 21 yes CT32B0_MAT3 PIO1_0 to PIO1_11 [5] R/PIO1_0/AD1/ 22 yes CT32B1_CAP0 [5] R/PIO1_1/AD2 CT32B1_MAT0 [5] no R/PIO1_2/AD3/ 24 CT32B1_MAT1 [5] SWDIO/PIO1_3 AD4/CT32B1_MAT2 [5] PIO1_4/AD5 CT32B1_MAT3/ WAKEUP [3] PIO1_5/RTS ...
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... NXP Semiconductors Table 10. LPC1100 and LPC1100L series: LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin Start logic input [3] PIO1_7/TXD CT32B0_MAT1 [3] PIO1_8 CT16B1_CAP0 [3] PIO1_9 CT16B1_MAT0 [5] PIO1_10/AD6 CT16B1_MAT1 [5] PIO1_11/AD7 27 no PIO2_0 [3] PIO2_0/DTR 1 no PIO3_0 to PIO3_5 [3] PIO3_2 28 no [3] PIO3_4 13 no ...
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... NXP Semiconductors Table 11. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 package) Symbol Pin Start logic input PIO0_0 to PIO0_11 [2] RESET/PIO0_0 3 yes [3] PIO0_1/CLKOUT/ 4 yes CT32B0_MAT2 [3] PIO0_2/SSEL0/ 10 yes CT16B0_CAP0 [3] PIO0_3 14 yes [4] PIO0_4/SCL 15 yes [4] PIO0_5/SDA 16 yes [3] PIO0_6/SCK0 22 yes [3] PIO0_7/CTS 23 yes [3] PIO0_8/MISO0/ 27 yes CT16B0_MAT0 [3] PIO0_9/MOSI0/ 28 yes ...
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... NXP Semiconductors Table 11. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 package) Symbol Pin Start logic input [5] R/PIO0_11/ 32 yes AD0/CT32B0_MAT3 PIO1_0 to PIO1_11 [5] R/PIO1_0/ 33 yes AD1/CT32B1_CAP0 [5] no R/PIO1_1/ 34 AD2/CT32B1_MAT0 [5] R/PIO1_2 AD3/CT32B1_MAT1 [5] SWDIO/PIO1_3 AD4/CT32B1_MAT2 [5] PIO1_4/AD5 CT32B1_MAT3/ WAKEUP [3] PIO1_5/RTS CT32B0_CAP0 [3] PIO1_6/RXD/ ...
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... NXP Semiconductors Table 11. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 package) Symbol Pin Start logic input [3] PIO1_7/TXD CT32B0_MAT1 [3] PIO1_8 CT16B1_CAP0 [3] PIO1_9 CT16B1_MAT0/ MOSI1 [5] PIO1_10/AD6 CT16B1_MAT1/ MISO1 [5] PIO1_11/AD7 CT32B1_CAP1 PIO2_0 to PIO2_11 [3] PIO2_0/DTR/SSEL1 2 no [3] PIO2_1/DSR/SCK1 13 no [3] PIO2_2/DCD/MISO1 26 no ...
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... NXP Semiconductors Table 11. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 package) Symbol Pin Start logic input [3] PIO2_7 CT32B0_MAT2/RXD [3] PIO2_8 CT32B0_MAT3/TXD [3] PIO2_9 CT32B0_CAP0 [3] PIO2_10 25 no [3] PIO2_11/SCK0 CT32B0_CAP1 PIO3_0 to PIO3_5 [3] PIO3_0/DTR CT16B0_MAT0/TXD [3] PIO3_1/DSR CT16B0_MAT1/RXD [3] PIO3_2/DCD CT16B0_MAT2/ ...
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... NXP Semiconductors Table 11. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 package) Symbol Pin Start logic input [6] XTALIN 6 - [6] XTALOUT [1] Pin state at reset for default function Input Output internal pull-up enabled (pins pulled up to full inactive, no pull-up/down enabled. ...
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... NXP Semiconductors Table 12. LPC1100XL series: LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin Start logic input PIO0_0 to PIO0_11 [2] RESET/PIO0_0 2 yes [3] PIO0_1/CLKOUT/ 3 yes CT32B0_MAT2 [3] PIO0_2/SSEL0/ 8 yes CT16B0_CAP0 [3] PIO0_3 9 yes [4] PIO0_4/SCL 10 yes [4] PIO0_5/SDA 11 yes [3] PIO0_6/SCK0 15 yes [3] PIO0_7/CTS 16 yes [3] PIO0_8/MISO0/ 17 yes CT16B0_MAT0 [3] PIO0_9/MOSI0/ 18 yes ...
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... NXP Semiconductors Table 12. LPC1100XL series: LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin Start logic input [5] R/PIO0_11/AD0/ 21 yes CT32B0_MAT3 PIO1_0 to PIO1_11 [5] R/PIO1_0/AD1/ 22 yes CT32B1_CAP0 [5] R/PIO1_1/AD2 CT32B1_MAT0 [5] no R/PIO1_2/AD3/ 24 CT32B1_MAT1 [5] SWDIO/PIO1_3 AD4/CT32B1_MAT2 [5] PIO1_4/AD5 CT32B1_MAT3/ WAKEUP [3] PIO1_5/RTS CT32B0_CAP0 [3] PIO1_6/RXD/ ...
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... NXP Semiconductors Table 12. LPC1100XL series: LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin Start logic input [3] PIO1_7/TXD CT32B0_MAT1 [3] PIO1_8 CT16B1_CAP0 [3] PIO1_9 CT16B1_MAT0/ MOSI [5] PIO1_10/AD6 CT16B1_MAT1/ MISO [5] PIO1_11/AD7 CT32B1_CAP1 PIO2_0 [3] PIO2_0/DTR 1 no PIO3_0 to PIO3_5 [3] PIO3_2 CT16B0_MAT2/ ...
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... NXP Semiconductors Table 12. LPC1100XL series: LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin Start logic input [6] XTALIN 4 - [6] XTALOUT [1] Pin state at reset for default function Input Output internal pull-up enabled (pins pulled up to full inactive, no pull-up/down enabled. ...
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... NXP Semiconductors 7. Functional description 7.1 ARM Cortex-M0 processor The ARM Cortex- general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.2 On-chip flash program memory The LPC1110/11/12/13/14/15 contain 64 kB (LPC1115 (LPC1114/333 (LPC1114/323 (LPC1114 (LPC1113 (LPC1112 (LPC1111 (LPC1110) of on-chip flash memory ...
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... NXP Semiconductors LPC1110/11/12/13/ reserved private peripheral bus reserved AHB peripherals reserved APB peripherals 1 GB reserved 0.5 GB reserved 16 kB boot ROM reserved 8 kB SRAM (LPC1113/14/301/302 SRAM (LPC1111/12/13/14/201/102/202 SRAM (LPC1111/12/101/002/102 SRAM (LPC1110) reserved 32 kB on-chip flash (LPC1114) ...
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... NXP Semiconductors LPC1111/12/13/14/15XL 4 GB reserved private peripheral bus reserved AHB peripherals reserved APB peripherals 1 GB reserved 0.5 GB reserved 16 kB boot ROM reserved 8 kB SRAM (LPC1113/14/15/303/323/333 SRAM (LPC1111/12/13/14/203 SRAM (LPC1111/12/103) reserved 64 kB on-chip flash (LPC1115 on-chip flash (LPC1114/333) ...
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... NXP Semiconductors • In the LPC1110/11/12/13/14/15, the NVIC supports 32 vectored interrupts including inputs to the start logic from individual GPIO pins. • Four programmable interrupt priority levels with hardware priority level masking. • Software interrupt generation. 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags ...
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... NXP Semiconductors • On the LPC1100L and LPC1100XL series, all GPIO pins (except PIO0_4 and PIO0_5) are pulled IOCONFIG block. • Programmable open-drain mode for series LPC1100L and LPC1100XL. 7.8 UART The LPC1110/11/12/13/14/15 contain one UART. Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode ...
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... NXP Semiconductors • Master or slave operation • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame 2 7.10 I C-bus serial I/O controller The LPC1110/11/12/13/14/15 contain one I Remark: Part LPC1112FDH20/102 does not contain the I 2 The I C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line (SCL) and a Serial DAta line (SDA) ...
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... NXP Semiconductors • Optional conversion on transition of input pin or timer match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. 7.12 General purpose external event counter/timers The LPC1110/11/12/13/14/15 include two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. ...
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... NXP Semiconductors • Flag to indicate watchdog reset. • Programmable 24-bit timer with internal prescaler. • Selectable time period from (T multiples of T • The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator (IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions ...
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... NXP Semiconductors See Figure 14 IRC oscillator watchdog oscillator IRC oscillator system oscillator SYSPLLCLKSEL (system PLL clock select) Fig 14. LPC1110/11/12/13/14/15 clock generation block diagram 7.16.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU ...
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... NXP Semiconductors 7.16.1.3 Watchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and temperature is 40 %. ...
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... NXP Semiconductors • Efficiency mode corresponding to optimized balance of current consumption and CPU performance. • Low-current mode corresponding to lowest power consumption. In addition, the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock. 7.16.5.2 Sleep mode When Sleep mode is entered, the clock to the core is stopped ...
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... NXP Semiconductors 7.17.2 Reset Reset has four sources on the LPC1110/11/12/13/14/15: the RESET pin, the Watchdog reset, Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller. ...
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... NXP Semiconductors CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be disabled. For details see the LPC111x user manual. 7.17.5 APB interface The APB peripherals are located on one APB bus. ...
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... NXP Semiconductors 8. Limiting values Table 13. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (core and external rail input voltage I I supply current DD I ground current SS I I/O latch-up current latch T storage temperature stg T maximum junction temperature ...
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... NXP Semiconductors 9. Static characteristics Table 14. Static characteristics = 40 C to +85 C, unless otherwise specified. T amb Symbol Parameter V supply voltage (core DD and external rail) LPC1100 series (LPC111x/101/201/301) power consumption I supply current DD LPC1100L series (LPC111x/002/102/202/302) power consumption in low-current mode I supply current DD LPC111X Product data sheet ...
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... NXP Semiconductors Table 14. Static characteristics = 40 C to +85 C, unless otherwise specified. T amb Symbol Parameter LPC1100XL series (LPC111x/103/203/303/323/333) power consumption in low-current mode I supply current DD Standard port pins, RESET I LOW-level input current HIGH-level input IH current I OFF-state output OZ current V input voltage I V output voltage ...
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... NXP Semiconductors Table 14. Static characteristics = 40 C to +85 C, unless otherwise specified. T amb Symbol Parameter V LOW-level output OL voltage I HIGH-level output OH current I LOW-level output OL current I HIGH-level short-circuit OHS output current I LOW-level short-circuit OLS output current I pull-down current pd I pull-up current pu High-drive output pin (PIO0_7) ...
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... NXP Semiconductors Table 14. Static characteristics = 40 C to +85 C, unless otherwise specified. T amb Symbol Parameter I HIGH-level output OH current I LOW-level output OL current I LOW-level short-circuit OLS output current I pull-down current pd I pull-up current C-bus pins (PIO0_4 and PIO0_5) V HIGH-level input IH voltage V LOW-level input voltage ...
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... NXP Semiconductors [10] WAKEUP pin pulled HIGH externally. [11] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. [12] Including voltage on outputs in 3-state mode. [13] V supply voltage must be present. DD [14] 3-state outputs go into 3-state mode in Deep power-down mode. [15] Allowed as long as the current limit does not exceed the maximum current allowed by the device. ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. ...
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... NXP Semiconductors 9.1 BOD static characteristics Table 16 C. T amb Symbol V th [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC111x user manual. LPC111X Product data sheet LPC1110/11/12/13/14/15 [1] BOD static characteristics Parameter Conditions threshold voltage interrupt level 0 ...
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... NXP Semiconductors 9.2 Power consumption LPC1100 series (LPC111x/101/201/301) Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC111x user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. • Configure GPIO pins as outputs using the GPIOnDIR registers. ...
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... NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 17. Active mode: Typical supply current I (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. ...
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... NXP Semiconductors (μA) Fig 19. Deep-sleep mode: Typical supply current I (μA) Fig 20. Deep power-down mode: Typical supply current I LPC111X Product data sheet −40 −15 Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). ...
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... NXP Semiconductors 9.3 Power consumption LPC1100L series (LPC111x/002/102/202/302) Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC111x user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. • Configure GPIO pins as outputs using the GPIOnDIR registers. ...
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... NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 22. Active mode: Typical supply current I (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. ...
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... NXP Semiconductors (μA) Fig 24. Deep-sleep mode: Typical supply current I (μA) Fig 25. Deep power-down mode: Typical supply current I LPC111X Product data sheet 5 4.5 3 3 2.5 1.5 −40 −15 Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). ...
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... NXP Semiconductors 9.4 Power consumption LPC1100XL series (LPC111x/103/203/303/323/333) Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC111x user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. • Configure GPIO pins as outputs using the GPIOnDIR registers. ...
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... NXP Semiconductors Fig 27. Active mode: Typical supply current I Fig 28. Sleep mode: Typical supply current I LPC111X Product data sheet (mA -40 -15 Conditions 3.3 V; active mode entered executing code DD disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. ...
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... NXP Semiconductors (μA) Fig 29. Deep-sleep mode: Typical supply current I (μA) Fig 30. Deep power-down mode: Typical supply current I LPC111X Product data sheet 5 4.5 3 3 2.5 1.5 −40 −15 Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). ...
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... NXP Semiconductors 9.5 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at T noted otherwise, the system oscillator and PLL are running in both measurements ...
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... NXP Semiconductors 9.6 Electrical pin characteristics V Fig 31. High-drive output: Typical HIGH-level output voltage V (mA) Fig 32. I LPC111X Product data sheet 3 °C (V) 25 °C −40 °C 3.2 2.8 2 Conditions 3 pin PIO0_7. DD output current 0.2 Conditions 3 pins PIO0_4 and PIO0_5. ...
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... NXP Semiconductors (mA) Fig 33. Typical LOW-level output current I V Fig 34. Typical HIGH-level output voltage V LPC111X Product data sheet 0.2 Conditions 3.3 V; standard port pins and PIO0_7. DD 3 °C 25 °C 3.2 −40 °C 2.8 2 Conditions 3.3 V; standard port pins All information provided in this document is subject to legal disclaimers. ...
Page 72
... NXP Semiconductors (μA) Fig 35. Typical pull-up current I (μA) Fig 36. Typical pull-down current I LPC111X Product data sheet −10 − °C 25 °C −40 °C −50 − Conditions 3.3 V; standard port pins. DD versus input voltage ° °C −40 °C ...
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... NXP Semiconductors 10. Dynamic characteristics 10.1 Power-up ramp conditions Table 18. = 40 C to +85 C. T amb Symbol Parameter wait V I [1] See [2] The wait time specifies the time the power supply must be at levels below 400 mV before ramping up. Fig 37. Power-up ramp 10.2 Flash memory Table 19. ...
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... NXP Semiconductors 10.3 External clock Table 20. = 40 C to +85 amb Symbol f osc T cy(clk) t CHCX t CLCX t CLCH t CHCL [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages ...
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... NXP Semiconductors 10.4 Internal oscillators Table 21. = 40 C to +85 C; 2.7 V amb Symbol f osc(RC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages. (MHz) Fig 39. Internal RC oscillator frequency versus temperature ...
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... NXP Semiconductors Table 22. Symbol Parameter f osc(int) Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [1] voltages. [2] The typical frequency spread over processing and temperature (T [3] See the LPC111x user manual. 10.5 I/O pins Table 23. = 40 C to +85 C; 3.0 V V ...
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... NXP Semiconductors 2 10.6 I C-bus Table 24. = 40 C to +85 C. T amb Symbol f SCL LOW t HIGH t HD;DAT t SU;DAT [1] See the I [2] Parameters are valid over operating temperature range unless otherwise specified. [3] t HD;DAT and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V (min) of the SCL signal) to bridge the undefined region of the falling edge of SCL ...
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... NXP Semiconductors SDA SCL SCL 2 Fig 40. I C-bus pins clock timing 10.7 SPI interfaces Table 25. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter SPI master (in SPI mode) T clock cycle time cy(clk) t data set-up time DS t data hold time ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 41. SPI master timing in SPI mode LPC111X Product data sheet T cy(clk) t v(Q) DATA VALID MOSI MISO DATA VALID t v(Q) DATA VALID MOSI DATA VALID MISO Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 42. SPI slave timing in SPI mode LPC111X Product data sheet T cy(clk) MOSI DATA VALID t MISO DATA VALID MOSI DATA VALID t v(Q) MISO DATA VALID Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. ...
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... NXP Semiconductors 11. Application information 11.1 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in • The ADC input trace must be short and as close as possible to the LPC1110/11/12/13/14/15 chip. • The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines. • ...
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... NXP Semiconductors Fig 44. Oscillator modes and models: oscillation mode of operation and external crystal Table 26. Fundamental oscillation frequency F 1 MHz to 5 MHz 5 MHz to 10 MHz 10 MHz to 15 MHz 15 MHz to 20 MHz Table 27. Fundamental oscillation frequency F 15 MHz to 20 MHz 20 MHz to 25 MHz 11 ...
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... NXP Semiconductors order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C accordingly to the increase in parasitics of the PCB layout. 11.4 Standard I/O pad configuration Figure 45 • Digital output driver • Digital input: Pull-up enabled/disabled • ...
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... NXP Semiconductors 11.5 Reset pad configuration Fig 46. Reset pad configuration 11.6 ElectroMagnetic Compatibility (EMC) Radiated emission measurements according to the IEC61967-2 standard using the TEM-cell method are shown for the LPC1114FBD48/302 in Table 28 3 Parameter Input clock: IRC (12 MHz) maximum peak level IEC level ...
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... NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
Page 87
... NXP Semiconductors TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
Page 88
... NXP Semiconductors DIP28: plastic dual in-line package; 28 leads (600 mil pin 1 index 1 DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. max. mm 5.1 0.51 4 inches 0.2 0.02 0.16 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (mm are the original dimensions) (1) (1) Unit max 0.05 0.30 mm nom 0.85 0.2 min 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (1) Unit max 1.00 0.05 0.35 mm nom 0.85 0.02 0.28 0.2 min 0.80 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Soldering solder lands occupied area Fig 54. Reflow soldering of the SO20 package LPC111X Product data sheet LPC1110/11/12/13/14/15 13.40 0.60 (20×) 1.50 8.00 1.27 (18×) placement accuracy ± 0.25 Dimensions in mm All information provided in this document is subject to legal disclaimers. Rev. 7 — 1 March 2012 32-bit ARM Cortex-M0 microcontroller 11 ...
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... NXP Semiconductors Footprint information for reflow soldering of TSSOP20 package solder land occupied area DIMENSIONS 0.650 0.750 7.200 4.500 1.350 Fig 55. Reflow soldering of the TSSOP20 package LPC111X Product data sheet (4x) P1 Generic footprint pattern Refer to the package outline drawing for actual layout ...
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... NXP Semiconductors Footprint information for reflow soldering of TSSOP28 package solder land occupied area DIMENSIONS 0.650 0.750 7.200 4.500 1.350 Fig 56. Reflow soldering of the TSSOP28 package LPC111X Product data sheet (4x) P1 Generic footprint pattern Refer to the package outline drawing for actual layout ...
Page 95
... NXP Semiconductors Footprint information for reflow soldering of HVQFN33 package solder land solder paste deposit occupied area Fig 57. Reflow soldering of the HVQFN33 package LPC111X Product data sheet OID = 8.20 OA PID = 7.25 PA+OA OwDtot = 5.10 OA evia = 4.25 0.20 SR chamfer (4×) SPD = 1.00 SP GapD = 0.70 SP evia = 2.40 SDhtot = 2.70 SP 4.55 SR DHS = 4.85 CU LbD = 5.80 CU LaD = 7.95 CU solder land plus solder paste ...
Page 96
... NXP Semiconductors Footprint information for reflow soldering of LQFP48 package solder land occupied area DIMENSIONS 0.500 0.560 10.350 10.350 7.350 Fig 58. Reflow soldering of the LQFP48 package LPC111X Product data sheet LPC1110/11/12/13/14/ (8× Generic footprint pattern ...
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... NXP Semiconductors 14. Abbreviations Table 29. Acronym ADC AHB APB BOD GPIO PLL RC SPI SSI SSP TEM UART LPC111X Product data sheet LPC1110/11/12/13/14/15 Abbreviations Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Peripheral Bus BrownOut Detection General Purpose Input/Output Phase-Locked Loop Resistor-Capacitor Serial Peripheral Interface ...
Page 98
... LPC1114FHN33/203, LPC1114FHN33/303, LPC1114FHI33/303, LPC1114FBD48/323, LPC1114FBD48/333, LPC1114FHN33/333, LPC1115FBD48/303). Product data sheet • Parts LPC1112FHI33/202 and LPC1114FHI33/302 added. • Parts LPC1112FDH28/102, LPC1114FDH28/102, LPC1114FN28/102, LPC1112FDH20/102, LPC1110FD20, LPC1111FDH20/002, LPC1112FD20/102 added. Product data sheet • ADC sampling frequency corrected in Table 7 (Table note 7). • Pull-up level specified in Table 3 to Table 4 and Section 7.7.1. ...
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... NXP Semiconductors Table 30. Revision history …continued Document ID Release date Modifications: LPC1111_12_13_14 v.1 20100416 LPC111X Product data sheet Data sheet status limit changed to 6500 V (min) /+6500 V (max) in Table 6. • V ESD • t updated for SPI in master mode (Table 17). DS • Deep-sleep mode functionality changed to allow BOD and watchdog oscillator as the only analog blocks allowed to remain running in Deep-sleep mode (Section 7.15.5.3). range changed to 3.0 V ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 9 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 16 7 Functional description . . . . . . . . . . . . . . . . . . 39 7.1 ARM Cortex-M0 processor . . . . . . . . . . . . . . . 39 7.2 On-chip flash program memory . . . . . . . . . . . 39 7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 39 7.4 Memory map 7.5 Nested Vectored Interrupt Controller (NVIC ...
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... NXP Semiconductors 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 100 16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 100 16.4 Trademarks 101 17 Contact information 101 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 LPC1110/11/12/13/14/15 32-bit ARM Cortex-M0 microcontroller Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. ...