LPC11E11FHN33 NXP Semiconductors, LPC11E11FHN33 Datasheet - Page 24

• Manufacturer Part Number: LPC11E11FHN33
• Description: The LPC11E1x are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existin
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC11E1X
Product data sheet
7.16.6.1 Reset
7.16.6.2 Brownout detection
7.16.6.3 Code security (Code Read Protection - CRP)
7.16.6 System control
Reset has four sources on the LPC11E1x: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip reset by any source, once the operating voltage attains
a usable level, starts the IRC and initializes the flash controller.
A LOW-going pulse as short as 50 ns resets the part.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
In Deep power-down mode, an external pull-up resistor is required on the RESET pin.
The LPC11E1x includes four levels for monitoring the voltage on the V
voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to
the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a
dedicated status register. Four additional threshold levels can be selected to cause a
forced reset of the chip.
CRP provides different levels of security in the system so that access to the on-chip flash
and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be
restricted. Programming a specific pattern into a dedicated flash location invokes CRP.
IAP commands are not affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details, see the LPC11Exx user manual.
There are three levels of Code Read Protection:
1. CRP1 disables access to the chip via the SWD and allows partial flash update
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
3. Running an application with level CRP3 selected, fully disables any access to the chip
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors cannot
be erased.
update using a reduced set of the ISP commands.
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin as well. If necessary, the application must provide a flash update
mechanism using IAP calls or using a call to the reinvoke ISP command to enable a
flash update via the USART.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 February 2012
32-bit ARM Cortex-M0 microcontroller
LPC11E1x
DD
© NXP B.V. 2012. All rights reserved.
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