LPC11U13FBD48 NXP Semiconductors, LPC11U13FBD48 Datasheet

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LPC11U1x 32-bit ARM Cortex-M0 microcontroller flash SRAM; USB device; USART Rev. 2 — 11 January 2012 1. General description The LPC11U1x are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller ...

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... NXP Semiconductors  Two GPIO grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.  High-current source output driver (20 mA) on one pin (P0_7).  High-current sink driver (20 mA) on true open-drain pins (P0_4 and P0_5).  ...

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... HVQFN33 LPC11U14FBD48/201 LQFP48 LPC11U14FET48/201 TFBGA48 4.1 Ordering options Table 2. Ordering options Type number Flash LPC11U12FHN33/201 16 kB LPC11U12FBD48/201 16 kB LPC11U13FBD48/201 24 kB LPC11U14FHN33/201 32 kB LPC11U14FHI33/201 32 kB LPC11U14FBD48/201 32 kB LPC11U14FET48/201 32 kB LPC11U1X Product data sheet Description plastic thermal enhanced very thin quad flat package; no leads; 33 terminals ...

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... NXP Semiconductors 5. Block diagram LPC11U12/13/14 HIGH-SPEED GPIO ports 0/1 GPIO RXD TXD (1) (1) DCD, DSR , RI SMARTCARD INTERFACE CTS, RTS, DTR SCLK CT16B0_MAT[1:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP0 CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 CT16B1_CAP0 CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 (1) CT32B0_CAP[1:0] CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 (2) CT32B1_CAP[1:0] WINDOWED WATCHDOG GPIO pins ...

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... NXP Semiconductors 6. Pinning information 6.1 Pinning PIO1_19/DTR/SSEL1 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE PIO0_20/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 Fig 2. Pin configuration (HVQFN33) LPC11U1X Product data sheet terminal 1 index area 1 2 RESET/PIO0_0 3 XTALIN 4 LPC11U1x XTALOUT Transparent top view All information provided in this document is subject to legal disclaimers. Rev. 2 — 11 January 2012 ...

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... NXP Semiconductors PIO1_25/CT32B0_MAT1 PIO1_19/DTR/SSEL1 RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE PIO0_20/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 PIO1_26/CT32B0_MAT2/RXD PIO1_27/CT32B0_MAT3/TXD Fig 3. Pin configuration (LQFP48) LPC11U1X Product data sheet XTALIN 6 LPC11U1x XTALOUT All information provided in this document is subject to legal disclaimers. Rev. 2 — 11 January 2012 LPC11U1x ...

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... NXP Semiconductors Fig 4. LPC11U1X Product data sheet ball A1 index area Pin configuration (TFBGA48) All information provided in this document is subject to legal disclaimers. Rev. 2 — 11 January 2012 LPC11U1x 32-bit ARM Cortex-M0 microcontroller LPC11U1x 002aag101 Transparent top view © ...

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... NXP Semiconductors 6.2 Pin description Table 3 number. The default function after reset is listed first. All port pins have internal pull-up resistors enabled after reset with the exception of the true open-drain pins PIO0_4 and PIO0_5. Every port pin has a corresponding IOCON register for programming the digital or analog function, the pull-up/pull-down configuration, the repeater, and the open-drain modes ...

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... NXP Semiconductors Table 3. Pin description Symbol PIO0_5/SDA PIO0_6/USB_CONNECT/ SCK0 PIO0_7/CTS PIO0_8/MISO0/ CT16B0_MAT0 PIO0_9/MOSI0/ CT16B0_MAT1 SWCLK/PIO0_10/SCK0/ CT16B0_MAT2 TDI/PIO0_11/AD0/ CT32B0_MAT3 LPC11U1X Product data sheet Reset Type state [1] [ I/O - I I I ...

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... NXP Semiconductors Table 3. Pin description Symbol TMS/PIO0_12/AD1/ CT32B1_CAP0 TDO/PIO0_13/AD2/ CT32B1_MAT0 TRST/PIO0_14/AD3/ CT32B1_MAT1 SWDIO/PIO0_15/AD4/ CT32B1_MAT2 PIO0_16/AD5/ CT32B1_MAT3/WAKEUP PIO0_17/RTS/ CT32B0_CAP0/SCLK LPC11U1X Product data sheet Reset Type state [ ...

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... NXP Semiconductors Table 3. Pin description Symbol PIO0_18/RXD/ CT32B0_MAT0 PIO0_19/TXD/ CT32B0_MAT1 PIO0_20/CT16B1_CAP0 PIO0_21/CT16B1_MAT0/ MOSI1 PIO0_22/AD6/ CT16B1_MAT1/MISO1 PIO0_23/AD7 PIO1_5/CT32B1_CAP1 PIO1_13/DTR/ CT16B0_MAT0/TXD LPC11U1X Product data sheet Reset Type state [ ...

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... NXP Semiconductors Table 3. Pin description Symbol PIO1_14/DSR/ CT16B0_MAT1/RXD PIO1_15/DCD/ CT16B0_MAT2/SCK1 PIO1_16/RI/ CT16B0_CAP0 PIO1_19/DTR/SSEL1 PIO1_20/DSR/SCK1 PIO1_21/DCD/MISO1 PIO1_22/RI/MOSI1 PIO1_23/CT16B1_MAT1/ SSEL1 LPC11U1X Product data sheet Reset Type state [ I ...

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... NXP Semiconductors Table 3. Pin description Symbol PIO1_24/CT32B0_MAT0 PIO1_25/CT32B0_MAT1 PIO1_26/CT32B0_MAT2/ RXD PIO1_27/CT32B0_MAT3/ TXD PIO1_28/CT32B0_CAP0/ SCLK PIO1_29/SCK0/ CT32B0_CAP1 PIO1_31 USB_DM USB_DP XTALIN XTALOUT LPC11U1X Product data sheet Reset Type state [ ...

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... NXP Semiconductors [1] Pin state at reset for default function Input Output internal pull-up enabled inactive, no pull-up/down enabled floating; floating pins, if not used, should be tied to ground or power to minimize power consumption. [2] See Figure 30 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode ...

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... NXP Semiconductors Table 4. Multiplexing of peripheral functions Peripheral Function CT16B1 CT16B1_CAP0 CT16B1_MAT0 CT16B1_MAT1 CT32B0 CT32B0_CAP0 CT32B0_CAP1 CT32B0_MAT0 CT32B0_MAT1 CT32B0_MAT2 CT32B0_MAT3 CT32B1 CT32B1_CAP0 CT32B1_CAP1 CT32B1_MAT0 CT32B1_MAT1 CT32B1_MAT2 CT32B1_MAT3 ADC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 USB USB_VBUS USB_FTOGGLE USB_CONNECT CLKOUT CLKOUT ...

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... NXP Semiconductors 7. Functional description 7.1 On-chip flash programming memory The LPC11U1x contain on-chip flash program memory. The flash can be programmed using In-System Programming (ISP) or In-Application Programming (IAP) via the on-chip boot loader software. 7.2 SRAM The LPC11U1x contain a total on-chip static RAM memory. ...

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... NXP Semiconductors LPC11U12/13/ reserved private peripheral bus reserved GPIO reserved APB peripherals 1 GB reserved 2 kB USB RAM reserved 0.5 GB reserved 16 kB boot ROM reserved 4 kB SRAM reserved 32 kB on-chip flash (LPC11U14 on-chip flash (LPC11U13 on-chip flash (LPC11U12 Fig 5. ...

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... NXP Semiconductors • Four programmable interrupt priority levels, with hardware priority level masking. • Software interrupt generation. 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source ...

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... NXP Semiconductors 7.7.1 Features • GPIO pins can be configured as input or output by software. • All GPIO pins default to inputs with interrupt disabled at reset. • Pin registers allow pins to be sensed and set individually. • eight GPIO pins can be selected from all GPIO pins to create an edge- or level-sensitive GPIO interrupt request. • ...

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... NXP Semiconductors The USART uses a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.9.1 Features • Maximum USART data bit rate of 3.125 Mbit/s. • 16-byte receive and transmit FIFOs. • Register locations conform to 16C550 industry standard. ...

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... NXP Semiconductors 7.11.1 Features • The I interface supports Fast-mode Plus with bit rates Mbit/s. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • ...

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... NXP Semiconductors • Four match registers per timer that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • four external outputs corresponding to match registers, with the following capabilities: – ...

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... NXP Semiconductors 7.16 Clocking and power control 7.16.1 Integrated oscillators The LPC11U1x include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following reset, the LPC11U1x will operate from the internal RC oscillator until switched by software ...

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... NXP Semiconductors IRC oscillator watchdog oscillator IRC oscillator system oscillator SYSPLLCLKSEL (system PLL clock select) system oscillator USBPLLCLKSEL (USB clock select) Fig 6. LPC11U1x clocking generation block diagram 7.16.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the system PLL and subsequently the CPU ...

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... NXP Semiconductors 7.16.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL. On the LPC11U1x, the system oscillator must be used to provide the clock source to USB. The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency the maximum CPU operating frequency, by the system PLL ...

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... NXP Semiconductors on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 7.16.5.1 Power profiles The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile ...

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... NXP Semiconductors Power-down mode reduces power consumption compared to Deep-sleep mode at the expense of longer wake-up times. 7.16.5.5 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip with the exception of the WAKEUP pin. The LPC11U1x can wake up from Deep power-down mode via the WAKEUP pin ...

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... NXP Semiconductors 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. ...

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... NXP Semiconductors 7.17 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is configured to support up to four breakpoints and two watch points. The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH) ...

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... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (core and DD external rail) V input voltage I I supply current DD I ground current SS I I/O latch-up current latch T storage temperature stg T maximum junction temperature ...

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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics    +85 C, unless otherwise specified. amb Symbol Parameter V supply voltage (core DD and external rail) I supply current DD Standard port pins, RESET I LOW-level input current HIGH-level input IH current I OFF-state output OZ current ...

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... NXP Semiconductors Table 6. Static characteristics    +85 C, unless otherwise specified. amb Symbol Parameter I LOW-level output OL current I HIGH-level short-circuit OHS output current I LOW-level short-circuit OLS output current I pull-down current pd I pull-up current pu High-drive output pin (PIO0_7) I LOW-level input current V ...

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... NXP Semiconductors Table 6. Static characteristics    +85 C, unless otherwise specified. amb Symbol Parameter 2 I C-bus pins (PIO0_4 and PIO0_5) V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys I LOW-level output OL current I LOW-level output OL current I input leakage current ...

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... NXP Semiconductors [7] USB_DP and USB_DM pulled LOW externally. [8] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. [9] IRC disabled; system oscillator enabled; system PLL enabled. [10] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode. ...

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... NXP Semiconductors Table 7. ADC static characteristics    +85 C unless otherwise specified; ADC frequency 4.5 MHz, V amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error ...

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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. ...

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... NXP Semiconductors 9.1 BOD static characteristics Table amb Symbol V th [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC11U1x user manual. 9.2 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC11U1x user manual): • ...

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... NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 8. (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 9. LPC11U1X Product data sheet ...

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... NXP Semiconductors (mA) (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 10. Typical supply current versus temperature in Sleep mode (μA) Fig 11. Typical supply current versus temperature in Deep-sleep mode LPC11U1X Product data sheet ...

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... NXP Semiconductors (μA) Fig 12. Typical supply current versus temperature in Power-down mode (μA) Fig 13. Typical supply current versus temperature in Deep power-down mode 9.3 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers ...

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... NXP Semiconductors Table 9. Peripheral IRC System oscillator at 12 MHz Watchdog oscillator at 500 kHz/2 BOD Main PLL ADC CLKOUT CT16B0 CT16B1 CT32B0 CT32B1 GPIO IOCONFIG I2C ROM SPI0 SPI1 UART WWDT USB LPC11U1X Product data sheet Power consumption for individual analog and digital blocks ...

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... NXP Semiconductors 9.4 Electrical pin characteristics V Fig 14. High-drive output: Typical HIGH-level output voltage V (mA) Fig 15. I LPC11U1X Product data sheet 3 °C (V) 25 °C −40 °C 3.2 2.8 2 Conditions 3 pin PIO0_7. DD output current 0.2 Conditions 3 pins PIO0_4 and PIO0_5. ...

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... NXP Semiconductors (mA) Fig 16. Typical LOW-level output current I V Fig 17. Typical HIGH-level output voltage V LPC11U1X Product data sheet 0.2 Conditions 3.3 V; standard port pins and PIO0_7. DD 3 °C 25 °C 3.2 −40 °C 2.8 2 Conditions 3.3 V; standard port pins All information provided in this document is subject to legal disclaimers. ...

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... NXP Semiconductors (μA) Fig 18. Typical pull-up current I (μA) Fig 19. Typical pull-down current I LPC11U1X Product data sheet −10 − °C 25 °C −40 °C −50 − Conditions 3.3 V; standard port pins. DD versus input voltage ° °C −40 °C ...

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... NXP Semiconductors 10. Dynamic characteristics 10.1 Flash memory Table 10.  amb Symbol N endu t ret prog [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. 10.2 External clock Table 11. ...

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... NXP Semiconductors 10.3 Internal oscillators Table 12.  amb Symbol f osc(RC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages. (MHz) Fig 21. Internal RC oscillator frequency versus temperature Table 13 ...

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... NXP Semiconductors 10.4 I/O pins Table 14.  amb Symbol [1] Applies to standard port pins and RESET pin. 2 10.5 I C-bus Table 15. Dynamic characteristic: I    [ +85 C. amb Symbol Parameter f SCL clock SCL frequency t fall time f t LOW period of the LOW ...

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... NXP Semiconductors could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of t [8] The maximum t HD;DAT transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (t VD;ACK SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. ...

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... NXP Semiconductors 10.6 SSP interface Table 16. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter SPI master (in SPI mode) T clock cycle time cy(clk) t data set-up time DS t data hold time DH t data output valid time in SPI mode v(Q) t data output hold time in SPI mode ...

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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 23. SSP master timing in SPI mode LPC11U1X Product data sheet T cy(clk) t v(Q) DATA VALID MOSI MISO DATA VALID t v(Q) DATA VALID MOSI t DATA VALID MISO All information provided in this document is subject to legal disclaimers. Rev. 2 — 11 January 2012 ...

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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 24. SSP slave timing in SPI mode LPC11U1X Product data sheet T cy(clk) MOSI DATA VALID t v(Q) MISO DATA VALID t MOSI DATA VALID t v(Q) MISO DATA VALID All information provided in this document is subject to legal disclaimers. Rev. 2 — 11 January 2012 ...

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... NXP Semiconductors 11. Application information 11.1 Suggested USB interface solutions LPC11Uxx Fig 25. USB interface on a self-powered device LPC11Uxx Fig 26. USB interface on a bus-powered device 11.2 XTAL input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF ...

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... NXP Semiconductors Fig 27. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. ...

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... NXP Semiconductors Table 17. Fundamental oscillation frequency F 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 18. Fundamental oscillation frequency F 15 MHz - 20 MHz 20 MHz - 25 MHz 11.3 XTAL Printed-Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors C third overtone crystal usage have a common ground plane ...

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... NXP Semiconductors 11.4 Standard I/O pad configuration Figure 29 • Digital output driver • Digital input: Pull-up enabled/disabled • Digital input: Pull-down enabled/disabled • Digital input: Repeater mode enabled/disabled • Analog input pin configured as digital output pin configured as digital input pin configured as analog input Fig 29 ...

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... NXP Semiconductors 11.5 Reset pad configuration Fig 30. Reset pad configuration 11.6 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in • The ADC input trace must be short and as close as possible to the LPC11U1x chip. ...

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... NXP Semiconductors 12. Package outline HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (1) Unit max 1.00 0.05 0.35 mm nom 0.85 0.02 0.28 0.2 min 0.80 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

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... NXP Semiconductors HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (mm are the original dimensions) (1) (1) Unit max 0.05 0.30 mm nom 0.85 0.2 min 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

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... NXP Semiconductors LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

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... NXP Semiconductors TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 x 4.5 x 0.7 mm ball A1 index area ball index area Dimensions Unit max 1.10 0.30 0.80 0.35 mm nom 0.95 0.25 0.70 0.30 min 0.85 0.20 0.65 0.25 Outline version IEC SOT1155-2 Fig 34. Package outline TFBGA48 (SOT1155-2) ...

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... NXP Semiconductors 13. Soldering Footprint information for reflow soldering of HVQFN33 package see detail X Hy solder land solder paste occupied area Dimensions 0.5 5.95 5.95 4.25 4.25 11-11-15 Issue date 11-11-20 Fig 35. Reflow soldering for the HVQFN33 (5x5) package LPC11U1X Product data sheet Hx Gx nSPx SLy Gy C SLx ...

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... NXP Semiconductors Footprint information for reflow soldering of HVQFN33 package solder land solder paste deposit occupied area Fig 36. Reflow soldering for the HVQFN33 (7x7) package LPC11U1X Product data sheet OID = 8.20 OA PID = 7.25 PA+OA OwDtot = 5.10 OA evia = 4.25 0.20 SR chamfer (4×) SPD = 1.00 SP GapD = 0.70 SP evia = 2.40 SDhtot = 2.70 SP 4.55 SR DHS = 4.85 CU LbD = 5.80 CU LaD = 7 ...

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... NXP Semiconductors Footprint information for reflow soldering of LQFP48 package solder land occupied area DIMENSIONS 0.500 0.560 10.350 10.350 7.350 Fig 37. Reflow soldering for the LQFP48 package LPC11U1X Product data sheet (8× Generic footprint pattern ...

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... NXP Semiconductors Footprint information for reflow soldering of TFBGA48 package P Hy solder land solder paste deposit solder land plus solder paste occupied area solder resist DIMENSIONS 0.50 0.225 0.275 0.325 Fig 38. Reflow soldering for the TFBGA48 package LPC11U1X Product data sheet ...

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... NXP Semiconductors 14. Abbreviations Table 19. Acronym A/D ADC AHB APB BOD GPIO JTAG PLL RC SPI SSI SSP TAP USART LPC11U1X Product data sheet Abbreviations Description Analog-to-Digital Analog-to-Digital Converter Advanced High-performance Bus Advanced Peripheral Bus BrownOut Detection General Purpose Input/Output Joint Test Action Group ...

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... NXP Semiconductors 15. Revision history Table 20. Revision history Document ID Release date LPC11U1X v.2 20120111 • Modifications: Number of physical and logical endpoints corrected in • Use of JTAG updated in • Sampling frequency corrected in • Conditions for parameter T • Part LPC11U14FHI33/201 added. • Editorial updates. • ROM-based integer division routines added • ...

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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Functional description . . . . . . . . . . . . . . . . . . 16 7.1 On-chip flash programming memory . . . . . . . 16 7.2 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.3 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.4 Memory map 7.5 Nested Vectored Interrupt Controller (NVIC ...