LPC1776FBD208 NXP Semiconductors, LPC1776FBD208 Datasheet - Page 46

• Manufacturer Part Number: LPC1776FBD208
• Description: The LPC1776 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC178X_7X
Objective data sheet
7.10.1 Features
7.11 General purpose DMA controller
The LPC178x/7x EMC is an ARM PrimeCell MultiPort Memory Controller peripheral
offering support for asynchronous static memory devices such as RAM, ROM, and flash.
In addition, it can be used as an interface with off-chip memory-mapped devices and
peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant
peripheral.
See
Note: Synchronous static memory devices (synchronous burst mode) are not supported.
The GPDMA is an AMBA AHB compliant peripheral allowing selected peripherals to have
DMA support.
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. The source and
destination areas can each be either a memory region or a peripheral and can be
accessed through the AHB master. The GPDMA controller allows data transfers between
the various on-chip SRAM areas and supports the SD/MMC card interface, all SSPs, the
I
triggered by selected timer match conditions. Memory-to-memory transfers and transfers
to or from GPIO are supported.
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S, all UARTs, the A/D Converter, and the D/A Converter peripherals. DMA can also be
Dynamic memory interface support including single data rate SDRAM.
Asynchronous static memory device support including RAM, ROM, and flash, with or
without asynchronous page mode.
Low transaction latency.
Read and write buffers to reduce latency and to improve performance.
8/16/32 data and 16/20/26 address lines wide static memory support.
16 bit and 32 bit wide chip select SDRAM memory support.
Static memory features include:
– Asynchronous page mode read
– Programmable Wait States
– Bus turnaround delay
– Output enable and write enable delays
– Extended wait
Four chip selects for synchronous memory and four chip selects for static memory
devices.
Power-saving modes dynamically control EMC_CKE and EMC_CLK outputs to
SDRAMs.
Dynamic memory self-refresh mode controlled by software.
Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row
address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB
parts, with 4, 8, 16, or 32 data bits per device.
Separate reset domains allow the for auto-refresh through a chip reset if desired.
Table 6
for EMC memory access.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 December 2011
32-bit ARM Cortex-M3 microcontroller
LPC178x/7x
© NXP B.V. 2011. All rights reserved.
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