LPC1776FET180 NXP Semiconductors, LPC1776FET180 Datasheet - Page 67

• Manufacturer Part Number: LPC1776FET180
• Description: The LPC1776 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC178X_7X
Objective data sheet
7.34.1 Reset
7.34.2 Brownout detection
7.34.3 Code security (Code Read Protection - CRP)
7.34 System control
Reset has four sources on the LPC178x/7x: the RESET pin, the Watchdog reset,
Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a
Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating
voltage attains a usable level, starts the Wake-up timer (see description in
Section
the oscillator is running, a fixed number of clocks have passed, and the flash controller
has completed its initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
The LPC178x/7x include 2-stage monitoring of the voltage on the V
voltage falls below <tbd> V, the BOD asserts an interrupt signal to the Vectored Interrupt
Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading
a dedicated status register.
The second stage of low-voltage detection asserts reset to inactivate the LPC178x/7x
when the voltage on the V
alteration of the flash as operation of the various elements of the chip would otherwise
become unreliable due to low voltage. The BOD circuit maintains this reset down below
1 V, at which point the power-on reset circuitry maintains the overall reset.
Both the <tbd> V and <tbd> V thresholds include some hysteresis. In normal operation,
this hysteresis allows the <tbd> V detection to reliably interrupt, or a regularly executed
event loop to sense the condition.
This feature of the LPC178x/7x allows user to enable different levels of security in the
system so that access to the on-chip flash and use of the JTAG and ISP can be restricted.
When needed, CRP is invoked by programming a specific pattern into a dedicated flash
location. IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection.
CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is
required and flash field updates are needed but all sectors can not be erased.
CRP2 disables access to chip via the JTAG and only allows full flash erase and update
using a reduced set of the ISP commands.
Running an application with level CRP3 selected fully disables any access to chip via the
JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too.
It is up to the user’s application to provide (if needed) flash update mechanism using IAP
calls or call reinvoke ISP command to enable flash update via UART0.
7.33.3), causing reset to remain asserted until the external Reset is de-asserted,
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 December 2011
DD(REG)(3V3)
pins falls below <tbd> V. This reset prevents
32-bit ARM Cortex-M3 microcontroller
LPC178x/7x
DD(REG)(3V3)
© NXP B.V. 2011. All rights reserved.
pins. If this
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