LPC1788FET208 NXP Semiconductors, LPC1788FET208 Datasheet - Page 2

• Manufacturer Part Number: LPC1788FET208
• Description: The LPC1788 is a Cortex-M3 microcontroller for embedded applications featuring a high level of integration and low power consumption at frequencies of 120 MHz
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC178X_7X
Objective data sheet
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Memory:
LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film
Transistors (TFT) displays.
External Memory Controller (EMC) provides support for asynchronous static memory
devices such as RAM, ROM and flash, as well as dynamic memories such as single
data rate SDRAM with an SDRAM clock of up to 80 MHz.
Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I2S, UART, CRC engine, Analog-to-Digital and
Digital-to-Analog converter peripherals, timer match signals, GPIO, and for
memory-to-memory transfers.
Serial interfaces:
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Cortex-M3 system tick timer, including an external clock input option.
Standard JTAG test/debug interface as well as Serial Wire Debug and Serial
WireTrace Port options.
Emulation trace module supports real-time trace.
Boundary scan for simplified board testing.
Non-maskable Interrupt (NMI) input.
Up to 512 kB on-chip flash program memory with In-System Programming (ISP)
and In-Application Programming (IAP) capabilities. The combination of an
enhanced flash memory accelerator and location of the flash memory on the CPU
local code/data bus provides high code performance from flash.
Up to 96 kB on-chip SRAM includes:
64 kB of SRAM on the CPU with local code/data bus for high-performance CPU
access.
Two 16 kB SRAM blocks with separate access paths for higher throughput. These
SRAM blocks may be used for DMA memory as well as for general purpose
instruction and data storage.
Up to 4032 byte on-chip EEPROM.
Dedicated DMA controller.
Selectable display resolution (up to 1024  768 pixels).
Supports up to 24-bit true-color mode.
Ethernet MAC with MII/RMII interface and associated DMA controller. These
functions reside on an independent AHB.
USB 2.0 full-speed dual-port device/host/OTG controller with on-chip PHY and
associated DMA controller.
Five UARTs with fractional baud rate generation, internal FIFO, DMA support, and
RS-485/EIA-485 support. One UART (UART1) has full modem control I/O, and one
UART (USART4) supports IrDA, synchronous mode, and a smart card mode
conforming to ISO7816-3.
Three SSP controllers with FIFO and multi-protocol capabilities. The SSP
controllers can be used with the GPDMA.
Three enhanced I
the full I
with standard port pins. Enhancements include multiple address recognition and
monitor mode.
I
with the GPDMA.
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S-bus (Inter-IC Sound) interface for digital audio input or output. It can be used
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C-bus specification and Fast-mode Plus with data rates of 1 Mbit/s, two
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 December 2011
2
C-bus interfaces, one with a true open-drain output supporting
32-bit ARM Cortex-M3 microcontroller
LPC178x/7x
© NXP B.V. 2011. All rights reserved.
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