LPC1857_53 NXP Semiconductors, LPC1857_53 Datasheet
LPC1857_53
Related parts for LPC1857_53
LPC1857_53 Summary of contents
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LPC1857/53 32-bit ARM Cortex-M3 MCU flash and 136 kB SRAM; Ethernet, two High-speed USB, LCD, EMC Rev. 1 — 14 December 2011 1. General description The LPC1857/53 are ARM Cortex-M3 based microcontrollers for embedded applications. The ...
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... GPIO registers are located on the AHB for fast access. GPIO ports have DMA support. GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources. LPC1857_53 Objective data sheet 2 C-bus interface with monitor mode and with open-drain I/O 2 C-bus specification ...
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... Power-On Reset (POR). Available as LQFP208, LBGA256, or TFBGA180 packages. 3. Applications Industrial Consumer White goods LPC1857_53 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 LPC1857/53 32-bit ARM Cortex-M3 microcontroller RFID readers e-Metering © ...
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... LPC1853FBD208 512 kB 256 kB LPC1857_53 Objective data sheet Description Plastic low profile ball grid array package; 256 balls; body 17 17 Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm Plastic low profile ball grid array package; 256 balls; body 17 17 Plastic low profile quad flat package ...
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... I S1 TIMER0 C_CAN1 TIMER1 SCU GPIO PIN INTERRUPTS GPIO GROUP0 INTERRUPT GPIO GROUP1 INTERRUPT = connected to GPDMA Fig 1. LPC1857/53 block diagram LPC1857_53 Objective data sheet HIGH-SPEED PHY HIGH- ETHERNET SPEED 10/100 GPDMA USB0 MAC HOST/ IEEE 1588 DEVICE/ OTG AHB MULTILAYER MATRIX ...
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... On the LPC1857/53, digital pins are grouped into 16 ports, named and PA to PF, with pins used per port. Each digital pin can support up to eight different digital functions, including General Purpose I/O (GPIO), selectable through the SCU registers. The pin name is not indicative of the GPIO port assigned to it. LPC1857_53 Objective data sheet 8 10 ...
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... Multiplexed digital pins P0_0 P0_1 P1_0 LPC1857_53 Objective data sheet Description [ I/O GPIO0[0] — General purpose digital input/output pin. I/O SSP1_MISO — Master In Slave Out for SSP1. I ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface — Function reserved — Function reserved — ...
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... P1_3 P1_4 LPC1857_53 Objective data sheet Description [ I/O GPIO0[8] — General purpose digital input/output pin. Boot pin (see Table 5). O CTOUT_7 — SCT output 7. Match output 3 of timer 1. I/O EMC_A6 — External memory address line — Function reserved. ...
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... P1_5 P1_6 P1_7 LPC1857_53 Objective data sheet Description [ I/O GPIO1[8] — General purpose digital input/output pin. O CTOUT_10 — SCT output 10. Match output 2 of timer — Function reserved. O EMC_CS0 — LOW active Chip Select 0 signal. O USB0_PWR_FAULT — Port power fault signal indicating overcurrent condition ...
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... P1_9 P1_10 P1_11 LPC1857_53 Objective data sheet Description [ I/O GPIO1[1] — General purpose digital input/output pin. O U1_DTR — Data Terminal Ready output for UART1. O CTOUT_12 — SCT output 12. Match output 0 of timer 3. I/O EMC_D1 — External memory data line — ...
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... R10 x 83 P1_14 R11 x 85 P1_15 T12 x 87 LPC1857_53 Objective data sheet Description [ I/O GPIO1[5] — General purpose digital input/output pin. I U1_DCD — Data Carrier Detect input for UART1 — Function reserved. I/O EMC_D5 — External memory data line 5. I T0_CAP1 — Capture input 1 of timer 0. ...
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... P1_17 P1_18 N12 x 95 P1_19 M11 x 96 LPC1857_53 Objective data sheet Description [ I/O GPIO0[3] — General purpose digital input/output pin. I U2_RXD — Receiver input for USART2 — Function reserved. I ENET_CRS — Ethernet Carrier Sense (MII interface). O T0_MAT0 — Match output 0 of timer 0. ...
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... M10 x 100 P2_0 T16 x 108 P2_1 N15 x 116 LPC1857_53 Objective data sheet Description [ I/O GPIO0[15] — General purpose digital input/output pin. I/O SSP1_SSEL — Slave Select for SSP1 — Function reserved. O ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface). I T0_CAP2 — Capture input 2 of timer 0. ...
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... P2_3 J12 x 127 P2_4 K11 x 128 LPC1857_53 Objective data sheet Description [ — Function reserved. I/O U0_UCLK — Serial clock input/output for USART0 in synchronous mode. I/O EMC_A11 — External memory address line 11. O USB0_IND1 — USB0 port indicator LED control output 1. ...
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... P2_6 K16 x 137 P2_7 H14 x 138 LPC1857_53 Objective data sheet Description [ — Function reserved. I CTIN_2 — SCT input 2. Capture input 2 of timer 0. I USB1_VBUS — Monitors the presence of USB1 bus power. Note: This signal must be HIGH for USB reset to occur. ...
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... P2_10 G16 x 146 P2_11 F16 x 148 LPC1857_53 Objective data sheet Description [ — Function reserved. Boot pin (see O CTOUT_0 — SCT output 0. Match output 0 of timer 0. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. I/O EMC_A8 — External memory address line 8. ...
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... E15 x 153 P2_13 C16 x 156 P3_0 F13 x 161 LPC1857_53 Objective data sheet Description [ I/O GPIO1[12] — General purpose digital input/output pin. O CTOUT_4 — SCT output 4. Match output 0 of timer — Function reserved. I/O EMC_A3 — External memory address line — Function reserved. ...
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... P3_2 F11 x 166 P3_3 B14 x 169 LPC1857_53 Objective data sheet Description [ I/O I2S0_TX_WS — Transmit Word Select driven by the master and received by the slave. Corresponds to the signal WS in the I specification. I/O I2S0_RX_WS — Receive Word Select driven by the master and received by the slave ...
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... P3_4 A15 x 171 P3_5 C12 x 173 P3_6 B13 x 174 LPC1857_53 Objective data sheet Description [ I/O GPIO1[14] — General purpose digital input/output pin — Function reserved — Function reserved. I/O SPIFI_SIO3 — I/O lane 3 for SPIFI. O U1_TXD — Transmitter output for UART1. I/O I2S0_TX_WS — Transmit Word Select driven by the master and received by the slave ...
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... P4_0 P4_1 LPC1857_53 Objective data sheet Description [ — Function reserved — Function reserved. I/O SSP0_MISO — Master In Slave Out for SSP0. I/O SPIFI_MOSI — Input 0 in SPIFI quad mode; SPIFI output IO0. I/O GPIO5[10] — General purpose digital input/output pin. ...
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... P4_3 P4_4 P4_5 LPC1857_53 Objective data sheet Description [ I/O GPIO2[2] — General purpose digital input/output pin. O CTOUT_0 — SCT output 0. Match output 0 of timer 0. O LCD_VD3 — LCD data — Function reserved — Function reserved. O LCD_VD12 — LCD data. ...
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... P4_7 P4_8 P4_9 LPC1857_53 Objective data sheet Description [ I/O GPIO2[6] — General purpose digital input/output pin. O CTOUT_4 — SCT output 4. Match output 0 of timer 1. O LCD_ENAB/LCDM — STN AC bias drive or TFT data enable input — Function reserved — Function reserved. ...
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... P5_0 P5_1 P5_2 LPC1857_53 Objective data sheet Description [ — Function reserved. I CTIN_2 — SCT input 2. Capture input 2 of timer 0. O LCD_VD10 — LCD data — Function reserved. I/O GPIO5[14] — General purpose digital input/output pin. O LCD_VD14 — LCD data. ...
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... P5_5 P10 x 81 P5_6 T13 x 89 LPC1857_53 Objective data sheet Description [ I/O GPIO2[12] — General purpose digital input/output pin. I MCI0 — Motor control PWM channel 0, input. I/O EMC_D15 — External memory data line 15 — Function reserved. I U1_RI — Ring Indicator input for UART1. ...
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... R12 x 91 P6_0 M12 x 105 P6_1 R15 x 107 LPC1857_53 Objective data sheet Description [ I/O GPIO2[7] — General purpose digital input/output pin. O MCOA2 — Motor control PWM channel 2, output A. I/O EMC_D11 — External memory data line 11 — Function reserved. I U1_RXD — Receiver input for UART1. ...
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... P6_3 P15 x 113 P6_4 R16 x 114 LPC1857_53 Objective data sheet Description [ I/O GPIO3[1] — General purpose digital input/output pin. O EMC_CKEOUT1 — SDRAM clock enable 1. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. I/O I2S0_RX_SDA — I read by the receiver. Corresponds to the signal SD in the I specification ...
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... P6_7 J13 x 123 P6_8 H13 x 125 LPC1857_53 Objective data sheet Description [ I/O GPIO3[4] — General purpose digital input/output pin. O CTOUT_6 — SCT output 6. Match output 2 of timer 1. I U0_RXD — Receiver input for USART0. O EMC_RAS — LOW active SDRAM Row Address Strobe. ...
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... P6_10 H15 x 142 P6_11 H12 x 143 P6_12 G15 x 145 LPC1857_53 Objective data sheet Description [ I/O GPIO3[5] — General purpose digital input/output pin — Function reserved — Function reserved. O EMC_DYCS0 — SDRAM chip select — Function reserved. O T2_MAT2 — Match output 2 of timer 2. ...
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... P7_1 C14 x 162 P7_2 A16 x 165 P7_3 C13 x 167 LPC1857_53 Objective data sheet Description [ I/O GPIO3[8] — General purpose digital input/output pin. O CTOUT_14 — SCT output 14. Match output 2 of timer — Function reserved. O LCD_LE — Line end signal — Function reserved. ...
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... Symbol P7_4 C8 x 189 P7_5 A7 x 191 P7_6 C7 x 194 LPC1857_53 Objective data sheet Description [ I/O GPIO3[12] — General purpose digital input/output pin. O CTOUT_13 — SCT output 13. Match output 1 of timer — Function reserved. O LCD_VD16 — LCD data. O LCD_VD4 — LCD data. ...
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... P8_0 P8_1 P8_2 LPC1857_53 Objective data sheet Description [ I/O GPIO3[15] — General purpose digital input/output pin. O CTOUT_8 — SCT output 8. Match output 0 of timer — Function reserved. O LCD_PWR — LCD panel power enable — Function reserved. ...
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... P8_4 P8_5 P8_6 LPC1857_53 Objective data sheet Description [ I/O GPIO4[3] — General purpose digital input/output pin. I/O USB1_ULPI_D2 — ULPI link bidirectional data line — Function reserved. O LCD_VD12 — LCD data. O LCD_VD19 — LCD data — Function reserved. ...
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... P8_8 P9_0 P9_1 LPC1857_53 Objective data sheet Description [ I/O GPIO4[7] — General purpose digital input/output pin. O USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt transfers to the PHY — Function reserved. O LCD_VD4 — LCD data. O LCD_PWR — LCD panel power enable. ...
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... P9_3 P9_4 N10 x 92 P9_5 LPC1857_53 Objective data sheet Description [ I/O GPIO4[14] — General purpose digital input/output pin. O MCOB2 — Motor control PWM channel 2, output — Function reserved — Function reserved. I/O I2S0_TX_SDA — I read by the receiver. Corresponds to the signal SD in the I specification ...
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... PA_1 J14 x 134 PA_2 K15 x 136 LPC1857_53 Objective data sheet Description [ I/O GPIO4[11] — General purpose digital input/output pin. O MCOB1 — Motor control PWM channel 1, output B. O USB1_PWR_FAULT — USB1 Port power fault signal indicating over-current condition; this signal monitors over-current on the USB1 bus (external circuitry required to detect over-current condition) ...
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... PA_4 G13 x 151 PB_0 B15 x 164 PB_1 A14 x 175 LPC1857_53 Objective data sheet Description [ I/O GPIO4[10] — General purpose digital input/output pin. I QEI_PHA — Quadrature Encoder Interface PHA input — Function reserved — Function reserved — Function reserved — Function reserved. ...
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... PB_3 A13 x 178 PB_4 B11 x 180 PB_5 A12 x 181 LPC1857_53 Objective data sheet Description [ — Function reserved. I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7. O LCD_VD21 — LCD data — Function reserved. I/O GPIO5[22] — General purpose digital input/output pin. ...
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... PC_0 PC_1 PC_2 LPC1857_53 Objective data sheet Description [ — Function reserved. I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3. O LCD_VD13 — LCD data — Function reserved. I/O GPIO5[26] — General purpose digital input/output pin. I CTIN_6 — SCT input 6. Capture input 1 of timer 3. ...
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... PC_5 PC_6 LPC1857_53 Objective data sheet Description [ I/O USB1_ULPI_D5 — ULPI link bidirectional data line — Function reserved. O U1_RTS — Request to Send output for UART1. Can also be configured RS-485/EIA-485 output enable signal for UART1. O ENET_TXD3 — Ethernet transmit data 3 (MII interface). ...
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... PC_8 PC_9 PC_10 LPC1857_53 Objective data sheet Description [ — Function reserved. I/O USB1_ULPI_D1 — ULPI link bidirectional data line — Function reserved. I ENET_RXD3 — Ethernet receive data 3 (MII interface). I/O GPIO6[6] — General purpose digital input/output pin — Function reserved. ...
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... PC_12 PC_13 PC_14 LPC1857_53 Objective data sheet Description [ — Function reserved. I USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line direction. I U1_DCD — Data Carrier Detect input for UART1 — Function reserved. I/O GPIO6[10] — General purpose digital input/output pin. ...
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... PD_1 PD_2 PD_3 LPC1857_53 Objective data sheet Description [ — Function reserved. O CTOUT_15 — SCT output 15. Match output 3 of timer 3. O EMC_DQMOUT2 — Data mask 2 used with SDRAM and static devices — Function reserved. I/O GPIO6[14] — General purpose digital input/output pin. ...
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... PD_5 PD_6 PD_7 LPC1857_53 Objective data sheet Description [ — Function reserved. O CTOUT_8 — SCT output 8. Match output 0 of timer 2. I/O EMC_D18 — External memory data line 18 — Function reserved. I/O GPIO6[18] — General purpose digital input/output pin — Function reserved. ...
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... PD_9 T11 - 84 PD_10 P11 - 86 PD_11 LPC1857_53 Objective data sheet Description [ — Function reserved. I CTIN_6 — SCT input 6. Capture input 1 of timer 3. I/O EMC_D22 — External memory data line 22 — Function reserved. I/O GPIO6[22] — General purpose digital input/output pin. ...
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... PD_13 T14 x 97 PD_14 R13 x 99 PD_15 T15 x 101 LPC1857_53 Objective data sheet Description [ — Function reserved — Function reserved. O EMC_CS2 — LOW active Chip Select 2 signal — Function reserved. I/O GPIO6[26] — General purpose digital input/output pin — Function reserved. ...
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... PE_0 P14 x 106 PE_1 N14 x 112 PE_2 M14 x 115 LPC1857_53 Objective data sheet Description [ — Function reserved — Function reserved. I/O EMC_A16 — External memory address line 16 — Function reserved. I/O GPIO6[30] — General purpose digital input/output pin. O SD_VOLT2 — SD/MMC bus voltage select output 2. ...
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... K13 x 120 PE_5 N16 - 122 PE_6 M16 - 124 LPC1857_53 Objective data sheet Description [ — Function reserved. O CAN0_TD — CAN transmitter output. I ADCTRIG1 — ADC trigger input 1. I/O EMC_A21 — External memory address line 21. I/O GPIO7[3] — General purpose digital input/output pin. ...
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... F14 - 150 PE_9 E16 - 152 PE_10 E14 - 154 LPC1857_53 Objective data sheet Description [ — Function reserved. O CTOUT_5 — SCT output 5. Match output 1 of timer 1. I U1_CTS — Clear to Send input for UART1. I/O EMC_D26 — External memory data line 26. ...
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... PE_12 D15 - - PE_13 G14 - - PE_14 C15 - - LPC1857_53 Objective data sheet Description [ — Function reserved. O CTOUT_12 — SCT output 12. Match output 0 of timer 3. O U1_TXD — Transmitter output for UART1. I/O EMC_D30 — External memory data line 30. I/O GPIO7[11] — General purpose digital input/output pin. ...
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... PF_0 D12 - 159 PF_1 E11 - - PF_2 D11 - 168 LPC1857_53 Objective data sheet Description [ — Function reserved. O CTOUT_0 — SCT output 0. Match output 0 of timer 0. 2 I/O I2C1_SCL — clock input/output (this pin does not use a 2 specialized I C pad). ...
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... PF_3 E10 - 170 PF_4 D10 x 172 PF_5 E9 - 190 LPC1857_53 Objective data sheet Description [ — Function reserved. I U3_RXD — Receiver input for USART3. I/O SSP0_MOSI — Master Out Slave in for SSP0 — Function reserved. I/O GPIO7[18] — General purpose digital input/output pin. ...
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... E7 - 192 PF_7 B7 - 193 PF_8 LPC1857_53 Objective data sheet Description [ — Function reserved. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. I/O SSP1_MISO — Master In Slave Out for SSP1. O TRACEDATA[1] — Trace data, bit 1. I/O GPIO7[20] — General purpose digital input/output pin. ...
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... PF_9 D6 - 203 PF_10 A3 - 205 PF_11 A2 - 207 LPC1857_53 Objective data sheet Description [ — Function reserved. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. O CTOUT_1 — SCT output 1. Match output 1 of timer — Function reserved. I/O GPIO7[23] — General purpose digital input/output pin. ...
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... CLK0 CLK1 T10 x - CLK2 D14 x 141 CLK3 P12 x - LPC1857_53 Objective data sheet Description [ EMC_CLK0 — SDRAM clock CLKOUT — Clock output pin — Function reserved — Function reserved. I/O SD_CLK — SD/MMC card clock. O EMC_CLK01 — SDRAM clock 0 and clock 1 combined. ...
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... WAKEUP3 ADC pins ADC0_0 ADC1_0/DAC LPC1857_53 Objective data sheet Description [ JTAG interface control signal. Also used for boundary scan. [ Test Clock for JTAG interface (default) or Serial Wire (SW) clock. [ Test Reset for JTAG interface. ...
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... VDDREG F10, x 135 F9, , L8, 188 L7 , 195 , 82, 33 LPC1857_53 Objective data sheet Description [ ADC input channel 1. Shared between 10-bit ADC0/1. [ ADC input channel 2. Shared between 10-bit ADC0/1. [ ADC input channel 3. Shared between 10-bit ADC0/1. [ ADC input channel 4 ...
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... DAC output, the pin is not 5 V tolerant. For analog functionality, disable the digital section of the pad by setting the pin to an input function and by disabling the pull-up resistor through the corresponding SFSP register. [ tolerant transparent analog pad. = 6.5 F and maximum resistance R [8] For maximum load C L VBUS = 0.2 V when longer driven. LPC1857_53 Objective data sheet Description [13 OTP programming voltage. [13 I/O power supply ...
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... V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis. [13] On the TFBGA180 and LQFP209 packages, VPP is internally connected to VDDIO. [14] On the LQFP208 package, VSSIO and VSS are connected to a common ground plane. LPC1857_53 Objective data sheet 2 C-bus Fast Mode Plus specification ...
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... The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical Reference Manual. 7.3 System Tick timer (SysTick) The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception interval. LPC1857_53 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 LPC1857/53 32-bit ARM Cortex-M3 microcontroller © ...
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... Controls system exceptions and peripheral interrupts. • In the LPC1857/53, the NVIC supports 53 vectored interrupts. • Eight programmable interrupt priority levels, with hardware priority level masking. • Relocatable vector table. LPC1857_53 Objective data sheet GPDMA ETHERNET USB0 0 1 All information provided in this document is subject to legal disclaimers. ...
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... A two-port flash accelerator maximizes the flash performance. LPC1857_53 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 ...
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... SPIFI 0 0 EMC 8-bit 0 0 EMC 16-bit 0 1 EMC 32-bit 0 1 LPC1857_53 Objective data sheet BOOT_SRC BOOT_SRC Description bit 1 bit The reset state of P1_1, P1_2, P2_8, and P2_9 pins determines the boot source. See 0 1 Boot from device connected to USART0 using pins P2_0 and P2_1 ...
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... Table 5. Boot mode USART0 SPIFI EMC 8-bit EMC 16-bit EMC 32-bit USB0 USB1 SPI (SSP) USART3 [1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI. LPC1857_53 Objective data sheet BOOT_SRC BOOT_SRC bit 1 bit ...
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... SRAM 0x1000 0000 Fig 6. LPC1857/53 Memory mapping (overview) LPC1857_53 Objective data sheet 4 GB 256 MB dynamic external memory DYCS3 256 MB dynamic external memory DYCS2 peripheral bit band alias region 1 GB 256 MB dynamic external memory DYCS1 ...
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APB3 ADC1 0x400E 4000 peripherals ADC0 0x400E 3000 C_CAN0 0x400E 2000 DAC 0x400E 1000 I2C1 0x400E 0000 0x400C 8000 GIMA 0x400C 7000 QEI 0x400C 6000 APB2 SSP1 0x400C 5000 peripherals timer3 0x400C 4000 timer2 0x400C ...
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... Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. • Direction control of individual bits. • All I/O default to inputs after reset. LPC1857_53 Objective data sheet be achieved. unchanged. All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 ...
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... Supports: – inputs – outputs – 16 match/capture registers – 16 events – 32 states LPC1857_53 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 LPC1857/53 32-bit ARM Cortex-M3 microcontroller © NXP B.V. 2011. All rights reserved. ...
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... After a few commands configure the interface at startup, the entire flash content is accessible as normal memory using byte, halfword, and word accesses by the processor and/or DMA channels. Simple sequences of commands handle erasure and programming. LPC1857_53 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 ...
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... Asynchronous page mode read – Programmable Wait States – Bus turnaround delay – Output enable and write enable delays – Extended wait LPC1857_53 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 LPC1857/53 32-bit ARM Cortex-M3 microcontroller © ...
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... Supports all full-speed USB-compliant peripherals. • Supports interrupts. • This module has its own, integrated DMA engine. LPC1857_53 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 LPC1857/53 32-bit ARM Cortex-M3 microcontroller © NXP B.V. 2011. All rights reserved. ...
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... Mbit/s • TCP/IP hardware checksum • IP checksum • DMA support LPC1857_53 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 LPC1857/53 32-bit ARM Cortex-M3 microcontroller © NXP B.V. 2011. All rights reserved 131 ...
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... USARTs support a synchronous mode and a smart card mode. The USARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. LPC1857_53 Objective data sheet full-duplex operation. input in full-duplex operation. ...
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... The I multi-master bus and can be controlled by more than one bus master connected to it. LPC1857_53 Objective data sheet All information provided in this document is subject to legal disclaimers. ...
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... Two DMA requests, controlled by programmable buffer levels. The DMA requests are connected to the GPDMA block. • Controls include reset, stop and mute options separately for I output. LPC1857_53 Objective data sheet 2 C-bus compliant bus interface with open-drain pins C-bus can be used for test and diagnostic purposes. ...
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... Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. LPC1857_53 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 LPC1857/53 32-bit ARM Cortex-M3 microcontroller © ...
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... Features • 32-bit counter. Counter can be free-running or be reset by a generated interrupt. • 32-bit compare value. LPC1857_53 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 LPC1857/53 32-bit ARM Cortex-M3 microcontroller © NXP B.V. 2011. All rights reserved. ...
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... Optional conversion on transition on ADCTRIG0 or ADCTRIG1 pins, combined timer outputs 8 or 15, or the PWM output MCOA2. • Individual result registers for each A/D channel to reduce interrupt overhead. • DMA support. LPC1857_53 Objective data sheet 256 cy(WDCLK) 4. cy(WDCLK) All information provided in this document is subject to legal disclaimers. ...
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... Timestamp values are taken from the RTC. • Runs in VBAT power domain, independent of system power supply. The event/recorder/monitor can therefore operate in Deep power-down mode. LPC1857_53 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 LPC1857/53 32-bit ARM Cortex-M3 microcontroller © ...
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... All branch clocks are outputs of one of two Clock Control Units (CCUs) and can be controlled independently. Branch clocks derived from the same base clock are synchronous in frequency and phase. LPC1857_53 Objective data sheet All information provided in this document is subject to legal disclaimers. ...
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... CREG block, the OTP controller, the back-up registers, and the event router) are located in the RTC power-domain. The main regulator or a battery supply can power the RTC. A power selector switch ensures that the RTC block is always powered on. LPC1857_53 Objective data sheet , 128 256 ...
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... Code security (Code Read Protection - CRP) CRP enables different levels of security so that access to the on-chip flash and use of the JTAG and ISP can be restricted. CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by CRP. LPC1857_53 Objective data sheet LPC18xx to I/O pads ...
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... JTAG debug and parallel trace functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four watch points. LPC1857_53 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 ...
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... Including voltage on outputs in 3-state mode. [3] The peak current is limited to 25 times the corresponding maximum current. [4] Dependent on package type. [5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. LPC1857_53 Objective data sheet [1] Conditions on pin VDDREG on pin VDDIO on pin VDDA ...
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... Table 7. Thermal characteristics 2 3 amb Symbol Parameter T maximum junction j(max) temperature LPC1857_53 Objective data sheet amb – = ambient temperature (C), = the package junction-to-ambient thermal resistance (C/W) = sum of internal and I/O power dissipation ...
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... V) I regulator supply current DD(REG)(3V3) (3 battery supply current BAT I I/O supply current DD(IO) I ADC supply current DD(ADC) LPC1857_53 Objective data sheet Conditions on pin VDDA on pin V ; LQFP100 DD package only Regulator supply active mode; code while(1){} executed from RAM; all peripherals disabled [2][3] CCLK = 12 MHz; PLL1 ...
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... HIGH-level output OH current I LOW-level output OL current I HIGH-level short-circuit OHS output current I LOW-level short-circuit OLS output current I pull-down current pd I pull-up current pu LPC1857_53 Objective data sheet …continued Conditions = 0 V; on-chip pull-up I resistor disabled on-chip I DD(IO) pull-down resistor disabled DD(IO) on-chip pull-up/down ...
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... OLS output current I/O pins - high drive strength: medium drive mode I HIGH-level output OH current I LOW-level output OL current I HIGH-level short-circuit OHS output current LPC1857_53 Objective data sheet …continued Conditions on I/O pins with analog function; analog function enabled = 0 V; on-chip pull-up I resistor disabled on-chip I DD(IO) ...
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... HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys V HIGH-level output OH voltage V LOW-level output OL voltage I HIGH-level output OH current LPC1857_53 Objective data sheet …continued Conditions drive LOW; connected to V DD(IO) 0 DD(IO 0 drive HIGH; connected to ground drive LOW; connected to V DD(IO) 0.4 V ...
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... V DD(REG)(3V3) DD(IO) DDA(3V3) [3] IRC enabled; PLL1 disabled. [4] IRC disabled; PLL1 enabled C. [5] On pin VBAT; T amb [6] V corresponds to the output of the power switch (see ps LPC1857_53 Objective data sheet …continued Conditions drive HIGH; connected to ground drive LOW; connected to V DD(IO DD(IO) ...
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... The weak pull-up resistor is connected to the V [13] The input cell disables the weak pull-up resistor when the applied input voltage exceeds V [14] The parameter value specified is a simulated value excluding bond capacitance. 10.1 Power consumption Fig 9. LPC1857_53 Objective data sheet rail and pulls up the I/O pin to the V DD(IO) X ...
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... NXP Semiconductors Fig 10. Typical supply current versus temperature in active mode Fig 11. Typical supply current versus temperature in sleep mode LPC1857_53 Objective data sheet <tbd> Conditions 3.0 V, normal mode entered executing code while (1){} from ROM; DD(REG)(3V3) internal pull-up resistors disabled; system PLL enabled; IRC enabled, BOD disabled; all peripherals disabled ...
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... NXP Semiconductors Fig 12. Typical supply current versus temperature in Deep-sleep mode Fig 13. Typical supply current versus temperature in Power-down mode LPC1857_53 Objective data sheet <tbd> Conditions BAT DD(IO ( <tbd> Conditions ...
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... Fig 14. Typical supply current versus temperature in Deep power-down mode 10.2 Electrical pin characteristics <tbd> Conditions: V DD(REG)(3V3) port pins. Fig 15. Typical HIGH-level output voltage V HIGH-level output source current I LPC1857_53 Objective data sheet <tbd> Conditions BAT DD(IO) 001aab173 ...
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... NXP Semiconductors (μA) Fig 17. Typical pull-up current I (μA) Fig 18. Typical pull-down current I LPC1857_53 Objective data sheet + - °C -40 °C -40 -60 - 3.3 V. Simulated data. Values C are typical values. Values at Conditions: V DD(IO 40 C correspond to minimum values. versus input voltage V ...
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... Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages. Fig 19. External clock timing (with an amplitude of at least V LPC1857_53 Objective data sheet Dynamic characteristic: Wake-up from Deep-sleep, Power-down, and Deep power-down modes ...
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... Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages. LPC1857_53 Objective data sheet Dynamic characteristic: oscillator + over specified ranges. ...
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... LOW period of the SCL clock LOW t HIGH period of the SCL clock HIGH t data hold time HD;DAT t data set-up time SU;DAT [1] Parameters are valid over operating temperature range unless otherwise specified. LPC1857_53 Objective data sheet <tbd> Conditions: Frequency values are typical values. ...
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... Fig 21. I C-bus pins clock timing 2 11.6 I S-bus interface Table 14 amb values. Symbol common to input and output LPC1857_53 Objective data sheet . f 2 C-bus system but the requirement t t SU;DAT HD;DAT LOW 2 Dynamic characteristics: I S-bus interface pins ...
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... I S-bus specification. I2Sx_TX_SCK I2Sx_TX_SDA I2Sx_TX_WS Fig 22. I I2Sx_RX_SCK I2Sx_RX_SDA I2Sx_RX_WS Fig 23. I LPC1857_53 Objective data sheet 2 Dynamic characteristics: I S-bus interface pins 3.3 V. Conditions and data refer to I2S0 and I2S1 pins. Simulated DD(REG)(3V3) Parameter Conditions data output valid time on pin I2Sx_TX_SDA ...
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... SCR) CPSDVSR [1] T cy(clk) main clock frequency f , the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 main register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register). LPC1857_53 Objective data sheet Conditions Min <tbd> [1] full-duplex mode - ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 24. SSP master timing in SPI mode LPC1857_53 Objective data sheet T cy(clk) t v(Q) DATA VALID MOSI MISO DATA VALID t v(Q) DATA VALID MOSI t DATA VALID MISO All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 25. SSP slave timing in SPI mode LPC1857_53 Objective data sheet T cy(clk) MOSI DATA VALID t v(Q) MISO DATA VALID t MOSI DATA VALID t v(Q) MISO DATA VALID All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 ...
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... WE HIGH to end of write WEHEOW time t BLS HIGH to data invalid BLSHDNV time t WE HIGH to address invalid WEHANV time t deactivation time deact t CS LOW to BLS LOW CSLBLSL LPC1857_53 Objective data sheet <tbd>. DD(REG)(3V3) [1] Conditions Min RD <tbd> <tbd> WAITOEN < ...
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... After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid. [5] End Of Write (EOW): Earliest of address invalid, EMC_CSx HIGH, EMC_BLSx HIGH (PB = 1). EMC_Ax EMC_CSx EMC_OE EMC_BLSx EMC_WE EMC_Dx Fig 26. External static memory read/write access ( LPC1857_53 Objective data sheet <tbd>. DD(REG)(3V3) [1] Conditions Min (WAITWR WAITWEN + 1) ...
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... LPC1857_53 Objective data sheet ...
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... Write cycle parameters t data output valid delay time d(QV) t data output hold time h(Q) LPC1857_53 Objective data sheet <tbd>. DD(REG)(3V3) Conditions All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 LPC1857/53 32-bit ARM Cortex-M3 microcontroller … ...
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... EOP width at receiver EOPR1 t EOP width at receiver EOPR2 [1] Characterized but not implemented as production test. Guaranteed by design. T PERIOD differential data lines Fig 29. Differential data-to-EOP transition skew and EOP width LPC1857_53 Objective data sheet , unless otherwise specified. DD(IO) Conditions see ...
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... The driver is active only the time. 11.10 Ethernet Table 20. amb Symbol Parameter RMII mode f clk clk LPC1857_53 Objective data sheet [1] Conditions on pin USB0_VDDA3V3_DRIVER; total supply current during transmit during receive with driver tri-stated on pin USB0_VDDA3V3_DRIVER; total supply current during transmit during receive ...
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... Output drivers can drive a load accommodating over 12 inch of PCB trace and the input [1] capacitance of the receiving device. [2] Timing values are given from the point at which the clock signal waveform crosses 1 the valid input or output level. Fig 30. Ethernet timing LPC1857_53 Objective data sheet Dynamic characteristics: Ethernet < ...
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... T = amb Symbol f clk t su(D) t h(D) t d(QV) t h(Q) Fig 31. SD/MMC timing LPC1857_53 Objective data sheet Dynamic characteristics: SD/MMC 3 3.6 V. Values guaranteed by design. DD(REG)(3V3) Parameter Conditions clock frequency on pin SD_CLK; data transfer mode on pin SD_CLK; identification mode data input set-up ...
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... T ADC and the ideal transfer curve. See = 25 C; maximum sampling frequency f [7] T amb [8] Input resistance R depends on the sampling frequency fs LPC1857_53 Objective data sheet +85 C; ADC frequency 4.5 MHz; unless otherwise specified. amb Conditions 2.7 V ...
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... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 32. 10-bit ADC characteristics LPC1857_53 Objective data sheet (2) (5) (4) (3) 1 LSB (ideal ...
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... L R load resistance L t settling time s [1] In the DAC CR register, bit BIAS = 0 (see the LPC18xx user manual). [2] Settling time is calculated within 1/2 LSB of the final value. LPC1857_53 Objective data sheet +85 C; unless otherwise specified amb Conditions 2.7 V V ...
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... LCD_VD14 - LCD_VD13 - LCD_VD12 - LCD_VD11 P4_9 LCD_VD10 P4_10 LCD_VD9 P4_8 LCD_VD8 P7_5 LCD_VD7 - LCD_VD6 - LCD_VD5 - LCD_VD4 - LCD_VD3 P4_2 LPC1857_53 Objective data sheet 8-bit mono STN single panel LCD function LPC18xx pin used - - - P8_4 - P8_5 - P8_6 - P8_7 UD[3] P4_2 UD[2] P4_3 UD[1] P4_4 UD[0] P4_1 LCDLP P7_6 ...
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... LCD_VD7 P8_4 RED3 LCD_VD6 P8_5 RED2 LCD_VD5 P8_6 RED1 LCD_VD4 P8_7 RED0 LCD_VD3 - - LCD_VD2 - - LCD_VD1 - - LPC1857_53 Objective data sheet 8-bit mono STN dual panel LCD function LPC18xx pin used UD[2] P4_3 UD[1] P4_4 UD[0] P4_1 LCDLP P7_6 LCDENAB/ P4_6 LCDM LCDFP P4_5 LCDDCLK P4_7 ...
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... C frequency). Capacitance C and must not be larger than 7 pF. Parameters F crystal manufacturer. Table 27. Fundamental oscillation frequency 2 MHz 4 MHz 8 MHz LPC1857_53 Objective data sheet TFT 16 bit (5:6:5 mode) TFT 16 bit (1:5:5:5 mode) TFT 24 bit LPC18xx LCD LPC18xx pin pin used function used ...
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... Table 28. Fundamental oscillation frequency 15 MHz 20 MHz Fig 33. Slave mode operation of the on-chip oscillator Fig 34. Oscillator modes with external crystal model used for C LPC1857_53 Objective data sheet Recommended values for C X1/X2 components parameters) low frequency mode Maximum crystal series resistance R < 160 ...
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... Also connect the external components to the ground plain. To keep the noise coupled in via the PCB as small as possible, make loops and parasitics as small as possible. Choose values of C increase in the PCB layout. LPC1857_53 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 ...
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... DIMENSIONS (mm are the original dimensions) A UNIT max 0.45 1.1 0.55 mm 1.55 0.35 0.9 0.45 OUTLINE VERSION IEC - - - SOT740-2 Fig 35. Package outline of the LBGA256 package LPC1857_53 Objective data sheet ∅ 1/2 e ∅ 1 scale ...
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... DIMENSIONS (mm are the original dimensions) UNIT max 1.20 0.40 0.80 mm nom 1.06 0.35 0.71 min 0.95 0.30 0.65 OUTLINE VERSION IEC SOT570-3 Fig 36. Package outline of the TFBGA180 package LPC1857_53 Objective data sheet ∅ 1 ∅ 1 ...
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... max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT459-1 136E30 Fig 37. Package outline of the LQFP208 package LPC1857_53 Objective data sheet X 105 104 ...
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... 1.00 0.450 0.450 0.600 17.500 17.500 Fig 38. Reflow soldering for the LBGA256 package LPC1857_53 Objective data sheet Hx P Generic footprint pattern Refer to the package outline drawing for actual layout Hx Hy All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 ...
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... 0.80 0.400 0.400 0.550 12.575 12.575 Fig 39. Reflow soldering for the TFBGA180 package LPC1857_53 Objective data sheet Hx P Generic footprint pattern Refer to the package outline drawing for actual layout Hx Hy All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 ...
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... DIMENSIONS 0.500 0.560 31.300 31.300 28.300 28.300 Fig 40. Reflow soldering for the LQFP208 package LPC1857_53 Objective data sheet Hx Gx (0.125 (8× Generic footprint pattern Refer to the package outline drawing for actual layout ...
Page 125
... PHY PLL PWM RMII SDRAM SPI SSI SSP TCP/IP TTL UART ULPI LPC1857_53 Objective data sheet Abbreviations Description Analog-to-Digital Converter Advanced Encryption Standard Advanced High-performance Bus Advanced Peripheral Bus Application Programming Interface BrownOut Detection Ball Grid Array Controller Area Network ...
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... NXP Semiconductors Table 29. Acronym USART USB UTMI LPC1857_53 Objective data sheet Abbreviations …continued Description Universal Synchronous Asynchronous Receiver/Transmitter Universal Serial Bus USB 2.0 Transceiver Macrocell Interface All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 LPC1857/53 32-bit ARM Cortex-M3 microcontroller © ...
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... NXP Semiconductors 17. Revision history Table 30. Revision history Document ID LPC1857_53 v.1 LPC1857_53 Objective data sheet Release date Data sheet status 20111214 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 December 2011 LPC1857/53 32-bit ARM Cortex-M3 microcontroller Change notice Supersedes ...
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... Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or LPC1857_53 Objective data sheet [3] Definition This document contains data from the objective specification for product development. ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s 19. Contact information For more information, please visit: For sales office addresses, please send an email to: LPC1857_53 Objective data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... General-Purpose DMA (GPDMA 7.15.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.15.3 SPI Flash Interface (SPIFI 7.15.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.15.4 SD/MMC card interface . . . . . . . . . . . . . . . . . 69 7.15.5 External Memory Controller (EMC 7.15.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.15.6 High-speed USB Host/Device/OTG interface (USB0 7.15.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 LPC1857_53 Objective data sheet 7.15.7 High-speed USB Host/Device interface with ULPI (USB1 7.15.7.1 Features 7.15.8 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . 71 7.15.8.1 Features 7.15.9 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.15.9.1 Features 7.16 Digital serial peripherals 7.16.1 UART ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 14 December 2011 Document identifier: LPC1857_53 ...