LPC2101_02_03 NXP Semiconductors, LPC2101_02_03 Datasheet
LPC2101_02_03
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LPC2101_02_03 Summary of contents
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LPC2101/02/03 Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB flash with ISP/IAP, fast ports and 10-bit ADC Rev. 04 — 2 June 2009 1. General description The LPC2101/02/03 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines ...
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... LPC2101FBD48 LPC2102FBD48 LPC2103FBD48 LPC2102FHN48 LPC2103FHN48 LPC2103FHN48H LPC2101_02_03_4 Product data sheet Description plastic low profile quad flat package; 48 leads; body 7 plastic low profile quad flat package; 48 leads; body 7 plastic low profile quad flat package; 48 leads; body 7 plastic thermal enhanced very thin quad flat package; no leads; ...
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... TIMER 2/TIMER 3 (1) 3 MAT2 (1) 4 MAT3 AD0[7:0] ADC GENERAL P0[31:0] PURPOSE I/O WATCHDOG TIMER (1) Pins shared with GPIO. Fig 1. Block diagram LPC2101_02_03_4 Product data sheet TMS TDI TRST TCK TDO TEST/DEBUG INTERFACE 8 kB ARM7TDMI-S AHB BRIDGE (Advanced High-performance Bus) MEMORY ACCELERATOR 8 kB/16 kB/ AHB TO APB ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning P0.19/MAT1.2/MISO1 P0.20/MAT1.3/MOSI1 P0.21/SSEL1/MAT3.0 P0.27/TRST/CAP2.0 P0.28/TMS/CAP2.1 P0.29/TCK/CAP2.2 Fig 2. LPC2101_02_03_4 Product data sheet VBAT 5 V DD(1V8) LPC2101FBD48 RST 6 LPC2102FBD48 V 7 LPC2103FBD48 XTAL1 12 XTAL2 Pin configuration (LQFP48) Rev. 04 — 2 June 2009 LPC2101/02/03 ...
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... NXP Semiconductors P0.19/MAT1.2/MISO1 P0.20/MAT1.3/MOSI1 P0.21/SSEL1/MAT3.0 P0.27/TRST/CAP2.0 Fig 3. LPC2101_02_03_4 Product data sheet terminal 1 index area VBAT DD(1V8) LPC2102FHN48 6 RST LPC2103FHN48 LPC2103FHN48H 8 P0.28/TMS/CAP2 P0.29/TCK/CAP2.2 XTAL1 11 XTAL2 12 Transparent top view Pin configuration (HVQFN48) Rev. 04 — 2 June 2009 ...
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... P0.9/RXD1/ 30 MAT2.2 [3] P0.10/RTS1/ 35 CAP1.0/AD0.3 LPC2101_02_03_4 Product data sheet Type Description I/O Port 0: Port 32-bit I/O port with individual direction controls for each bit. A total of 31 pins of the Port 0 can be used as general purpose bidirectional digital I/Os while P0. output only pin. The operation of port 0 pins depends upon the pin function selected via the pin connect block ...
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... SDA1 [1] P0.19/MAT1.2/ 1 MISO1 [1] P0.20/MAT1.3/ 2 MOSI1 [1] P0.21/SSEL1/ 3 MAT3.0 LPC2101_02_03_4 Product data sheet Type Description I/O P0.11 — General purpose input/output digital pin. I CTS1 — Clear to Send input for UART1. I CAP1.1 — Capture input for Timer 1, channel 1. I AD0.4 — ADC 0, input 4. I/O P0.12 — General purpose input/output digital pin. ...
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... RTCX2 25 [7] RTCK 26 XTAL1 11 XTAL2 12 DBGSEL 27 RST 6 LPC2101_02_03_4 Product data sheet Type Description I/O P0.22 — General purpose input/output digital pin. I AD0.0 — ADC 0, input 0. I/O P0.23 — General purpose input/output digital pin. I AD0.1 — ADC 0, input 1. I/O P0.24 — General purpose input/output digital pin. I AD0.2 — ADC 0, input 2. ...
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... Open-drain configuration applies only to I [7] Pad provides special analog functionality. [8] For lowest power consumption, pin should be left floating when the RTC is not used. [9] See LPC2101/02/03 User manual UM10161 for details. LPC2101_02_03_4 Product data sheet Type Description I Ground reference. I Analog ground reference ...
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... The entire flash memory is available for user code as the bootloader resides in a separate memory. The LPC2101/02/03 flash memory provides a minimum of 100,000 erase/write cycles and 20 years of data-retention memory. LPC2101_02_03_4 Product data sheet Single-chip 16-bit/32-bit microcontrollers Rev. 04 — 2 June 2009 LPC2101/02/03 © ...
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... The LPC2101/02/03 memory map incorporates several distinct regions, as shown in Figure 4. In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either flash memory (the default) or on-chip static RAM. This is described in “System Fig 4. LPC2101_02_03_4 Product data sheet control”. 4.0 GB AHB PERIPHERALS 3.75 GB APB PERIPHERALS 3 ...
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... After reset all pins of Port 0 are configured as input with the following exceptions: If the DBGSEL pin is HIGH (Debug mode enabled), the JTAG pins will assume their JTAG functionality for use with EmbeddedICE and cannot be configured via the pin connect block. LPC2101_02_03_4 Product data sheet Single-chip 16-bit/32-bit microcontrollers Rev. 04 — 2 June 2009 LPC2101/02/03 © ...
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... Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points and 14 bytes LPC2101_02_03_4 Product data sheet Single-chip 16-bit/32-bit microcontrollers Rev. 04 — 2 June 2009 LPC2101/02/03 © NXP B.V. 2009. All rights reserved. ...
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... Features • Compliant with SPI specification. • Synchronous, Serial, Full Duplex, Communication. LPC2101_02_03_4 Product data sheet 2 C-bus interface. 2 C-bus can also be used for test and diagnostic purposes. Rev. 04 — 2 June 2009 ...
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... Reset timer on match with optional interrupt generation. • Four external outputs per timer/counter corresponding to match registers, with the following capabilities: – Set LOW on match. LPC2101_02_03_4 Product data sheet Single-chip 16-bit/32-bit microcontrollers Rev. 04 — 2 June 2009 LPC2101/02/03 © NXP B.V. 2009. All rights reserved. ...
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... Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. LPC2101_02_03_4 Product data sheet Single-chip 16-bit/32-bit microcontrollers Rev. 04 — 2 June 2009 LPC2101/02/03 © NXP B.V. 2009. All rights reserved ...
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... The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s. LPC2101_02_03_4 Product data sheet 256 PCLK 4 ...
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... V and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. LPC2101_02_03_4 Product data sheet Single-chip 16-bit/32-bit microcontrollers ramp (in the case of power on), the type of crystal DD Rev. 04 — ...
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... RAM. This allows code running in different memory spaces to have control of the interrupts. 6.17.7 Power control The LPC2101/02/03 supports three reduced power modes: Idle mode, Power-down mode, and Deep power-down mode. LPC2101_02_03_4 Product data sheet Single-chip 16-bit/32-bit microcontrollers Rev. 04 — 2 June 2009 LPC2101/02/03 © ...
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... Because the APB divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode. 6.18 Emulation and debugging The LPC2101/02/03 support emulation and debugging via a JTAG serial port. LPC2101_02_03_4 Product data sheet DD(1V8 the processor clock rate ...
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... lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2101/02/03 contain a specific configuration of RealMonitor software programmed into the on-chip boot ROM memory. LPC2101_02_03_4 Product data sheet Single-chip 16-bit/32-bit microcontrollers 1 of the CPU clock (CCLK) for the JTAG interface to operate ...
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... Per supply pin. [9] The peak current is limited to 25 times the corresponding maximum current. [10] Per ground pin. [11] Dependent on package type. [12] Performed per AEC-Q100-002. [13] Performed per AEC-Q100-003. [14] Performed per AEC-Q100-011. LPC2101_02_03_4 Product data sheet Single-chip 16-bit/32-bit microcontrollers [1] Conditions [2] [3] for the RTC ...
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... LOW-level output OL voltage I HIGH-level output OH current I LOW-level output OL current I HIGH-level OHS short-circuit output current I LOW-level OLS short-circuit output current I pull-down current pd LPC2101_02_03_4 Product data sheet Conditions pull- pull-down I DD(3V3 DD(3V3) pull-up/down (0.5V ) < V < (1.5V DD(3V3) I ...
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... V hysteresis voltage hys V LOW-level output OL voltage I input leakage LI current Oscillator pins V input voltage on pin i(XTAL1) XTAL1 LPC2101_02_03_4 Product data sheet …continued Conditions [12] V < V < DD(3V3) I Active mode; code while(1){} executed from flash; all peripherals enabled via PCONP register but not confi ...
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... See [7] The absolute error ( the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC T and the ideal transfer curve. See LPC2101_02_03_4 Product data sheet …continued Conditions drops below 1 grounded. ...
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... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 5. ADC conversion characteristics LPC2101_02_03_4 Product data sheet (2) (5) (4) (3) 1 LSB (ideal) 1018 ...
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... NXP Semiconductors 8.1 Power consumption in Deep power-down mode I DD(CORE Fig 6. I BAT ( A Fig 7. LPC2101_02_03_4 Product data sheet 1.5 1.25 1 0.75 0 Test conditions: Deep power-down mode entered; RTC off; SRAM off 3.3 V. i(VBAT) DD(3V3) DDA Core supply current I measured at different temperatures and supply ...
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... NXP Semiconductors I DD(IO Fig 8. LPC2101_02_03_4 Product data sheet 0.20 0.15 0.10 0. Test conditions: Deep power-down mode entered; RTC off; SRAM off 1 3.3 V. DD(1V8) i(BAT) DDA I/O supply current I measured at different temperatures DD(IO) Rev. 04 — 2 June 2009 LPC2101/02/03 Single-chip 16-bit/32-bit microcontrollers 002aae682 ...
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... C = 100 pF. To limit the input voltage to the specified range, choose an additional i capacitor to ground C mode, a minimum of 200 mV (RMS) is needed. For more details see the LPC2101/02/03 User manual UM10161 . Fig 9. LPC2101_02_03_4 Product data sheet Conditions which attenuates the input voltage by a factor C ...
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... Loops must be made as small as possible, in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C smaller accordingly to the increase in parasitics of the PCB layout. LPC2101_02_03_4 Product data sheet Single-chip 16-bit/32-bit microcontrollers Rev. 04 — 2 June 2009 ...
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... UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT313-2 136E05 Fig 10. Package outline SOT313-2 (LQFP48) LPC2101_02_03_4 Product data sheet ...
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... A UNIT max 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included OUTLINE VERSION IEC SOT619 Fig 11. Package outline SOT619-7 (HVQFN48) LPC2101_02_03_4 Product data sheet 1 1 (1) (1) ...
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... A UNIT max 0.05 0. 0.2 0.00 0.15 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included OUTLINE VERSION IEC SOT778 Fig 12. Package outline SOT778-3 (HVQFN48) LPC2101_02_03_4 Product data sheet 1 1 ...
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... IRQ ISP PLL PWM SPI SRAM SSI SSP TTL UART VIC LPC2101_02_03_4 Product data sheet Acronym list Description Analog-to-Digital Converter Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Debug Communications Channel Digital Signal Processor First In, First Out Fast Interrupt reQuest General Purpose Input/Output ...
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... Voltage range for pins V DD(3V3) Product data sheet DDA DD(act) Preliminary data sheet Preliminary data sheet Rev. 04 — 2 June 2009 LPC2101/02/03 Single-chip 16-bit/32-bit microcontrollers Change Supersedes notice LPC2101_02_03_3 CRP)”: added description of three . hys and V extended to 2.6 V. DDA - LPC2101_02_03_2 and V . DD(1V8 ...
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... NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 15. Contact information For more information, please visit: For sales office addresses, please send an email to: LPC2101_02_03_4 Product data sheet [3] Definition This document contains data from the objective specification for product development. ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: LPC2101_02_03_4 All rights reserved. Date of release: 2 June 2009 ...