LPC2387FBD100 NXP Semiconductors, LPC2387FBD100 Datasheet
LPC2387FBD100
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LPC2387FBD100 Summary of contents
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LPC2387 Single-chip 16-bit/32-bit MCU; 512 kB flash with ISP/IAP, Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC Rev. 5 — 9 January 2012 1. General description The LPC2387 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that ...
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... NXP Semiconductors Serial interfaces: Ethernet MAC with associated DMA controller. These functions reside on an independent AHB. USB 2.0 device/host/OTG with on-chip PHY and associated DMA controller. Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO. ...
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... Type number Package Name LPC2387FBD100 LQFP100 4.1 Ordering options Table 2. Ordering options Type number Flash (kB) Local bus LPC2387FBD100 512 64 LPC2387 Product data sheet Description plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SRAM (kB) Ether net Ethernet GP/ RTC Total buffers ...
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... NXP Semiconductors 5. Block diagram LPC2387 P0, P1, P2, P3, P4 HIGH-SPEED GPIO 70 PINS TOTAL ETHERNET RMII(8) MAC WITH DMA EINT3 to EINT0 EXTERNAL INTERRUPTS P0 × CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 × MAT2, TIMER2/TIMER3 2 × MAT0/MAT1/ MAT3 6 × PWM1 2 × PCAP1 LEGACY GPI/O P0 PINS TOTAL 6 × ...
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... P0[4]/I2SRX_CLK/ 81 RD2/CAP2[0] LPC2387 Product data sheet 1 LPC2387FBD100 25 Type Description I/O Port 0: Port 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. Pins 12, 13, 14, and 31 of this port are not available. ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin [1] P0[5]/I2SRX_WS/ 80 TD2/CAP2[1] [1] P0[6]/I2SRX_SDA/ 79 SSEL1/MAT2[0] [1] P0[7]/I2STX_CLK/ 78 SCK1/MAT2[1] [1] P0[8]/I2STX_WS/ 77 MISO1/MAT2[2] [1] P0[9]/I2STX_SDA/ 76 MOSI1/MAT2[3] [1] P0[10]/TXD2/ 48 SDA2/MAT3[0] [1] P0[11]/RXD2/ 49 SCL2/MAT3[1] [1] P0[15]/TXD1/ 62 SCK0/SCK [1] P0[16]/RXD1/ 63 SSEL0/SSEL LPC2387 Product data sheet Type Description I/O P0[5] — General purpose digital input/output pin. I/O I2SRX_WS — Receive Word Select driven by the master and received by the slave ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin [1] P0[17]/CTS1/ 61 MISO0/MISO [1] P0[18]/DCD1/ 60 MOSI0/MOSI [1] P0[19]/DSR1/ 59 MCICLK/SDA1 [1] P0[20]/DTR1/ 58 MCICMD/SCL1 [1] P0[21]/RI1/ 57 MCIPWR/RD1 [1] P0[22]/RTS1/ 56 MCIDAT0/TD1 [2] P0[23]/AD0[0]/ 9 I2SRX_CLK/ CAP3[0] [2] P0[24]/AD0[1]/ 8 I2SRX_WS/ CAP3[1] [2] P0[25]/AD0[2]/ 7 I2SRX_SDA/ TXD3 LPC2387 Product data sheet Type Description I/O P0[17] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin [3] P0[26]/AD0[3]/ 6 AOUT/RXD3 [4] P0[27]/SDA0 25 [4] P0[28]/SCL0 24 [5] P0[29]/USB_D+ 29 [5] P0[30]/USB_D 30 P1[0] to P1[31] [1] P1[0]/ENET_TXD0 95 [1] P1[1]/ENET_TXD1 94 [1] P1[4]/ENET_TX_EN 93 [1] P1[8]/ENET_CRS 92 [1] P1[9]/ENET_RXD0 91 [1] P1[10]/ENET_RXD1 90 [1] P1[14]/ 89 ENET_RX_ER [1] P1[15]/ 88 ENET_REF_CLK [1] P1[16]/ENET_MDC 87 [1] P1[17]/ENET_MDIO 86 LPC2387 Product data sheet ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin [1] P1[18]/ 32 USB_UP_LED/ PWM1[1]/ CAP1[0] [1] P1[19]/ 33 USB_TX_E1/ USB_PPWR1/ CAP1[1] [1] P1[20]/ 34 USB_TX_DP1/ PWM1[2]/SCK0 [1] P1[21]/ 35 USB_TX_DM1/ PWM1[3]/SSEL0 [1] P1[22]/ 36 USB_RCV1/ USB_PWRD1/ MAT1[0] [1] P1[23]/ 37 USB_RX_DP1/ PWM1[4]/MISO0 [1] P1[24]/ 38 USB_RX_DM1/ PWM1[5]/MOSI0 [1] P1[25]/ 39 USB_LS1/ USB_HSTEN1/ MAT1[1] [1] P1[26]/ 40 ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin [1] P1[27]/ 43 USB_INT1/ USB_OVRCR1/ CAP0[1] [1] P1[28]/USB_SCL1/ 44 PCAP1[0]/MAT0[0] [1] P1[29]/USB_SDA1/ 45 PCAP1[1]/MAT0[1] [2] P1[30]/V /AD0[4] 21 BUS [2] P1[31]/SCK1/AD0[5] 20 P2[0] to P2[31] [1] P2[0]/PWM1[1]/ 75 TXD1/TRACECLK [1] P2[1]/PWM1[2]/ 74 RXD1/PIPESTAT0 [1] P2[2]/PWM1[3]/ 73 CTS1/PIPESTAT1 [1] P2[3]/PWM1[4]/ 70 DCD1/PIPESTAT2 LPC2387 Product data sheet Type Description I/O P1[27] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin [1] P2[4]/PWM1[5]/ 69 DSR1/TRACESYNC [1] P2[5]/PWM1[6]/ 68 DTR1/TRACEPKT0 [1] P2[6]/PCAP1[0]/RI1/ 67 TRACEPKT1 [1] P2[7]/RD2/ 66 RTS1/TRACEPKT2 [1] P2[8]/TD2/ 65 TXD2/TRACEPKT3 [1] P2[9]/ 64 USB_CONNECT/ RXD2/EXTIN0 [6] P2[10]/EINT0 53 [6] P2[11]/EINT1/ 52 MCIDAT1/ I2STX_CLK [6] P2[12]/EINT2/ 51 MCIDAT2/ I2STX_WS LPC2387 Product data sheet Type Description I/O P2[4] — General purpose digital input/output pin. ...
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... O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2387 being in Reset state. Note: This pin is available in LPC2387FBD100 devices only (LQFP100 package). I External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0 ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin V 15, 31, SS 41, 55, 72, 97, [13] 83 [14 SSA V 28, 54, DD(3V3) [15] 71 13, 42, DD(DCDC)(3V3) [16] 84 [17 DDA [17] VREF 12 [17] VBAT 19 [ tolerant pad providing digital I/O functions with TTL levels and hysteresis. [ tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a DAC input, digital section of the pad is disabled ...
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... NXP Semiconductors 7. Functional description 7.1 Architectural overview The LPC2387 microcontroller consists of an ARM7TDMI-S CPU with emulation support, the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip memory, the AMBA AHB interfacing to high-speed on-chip peripherals, and the AMBA APB for connection to other on-chip peripheral functions. The microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte order ...
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... NXP Semiconductors The Thumb set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. ...
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... NXP Semiconductors 3.75 GB Fig 3. 7.5 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt ReQuest (IRQ) and Fast Interrupt ReQuest (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...
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... NXP Semiconductors FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device ...
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... NXP Semiconductors • Single DMA and burst DMA request signals. Each peripheral connected to the GPDMA can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the GPDMA. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers. • ...
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... NXP Semiconductors Additionally, any pin on port 0 and port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode ...
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... NXP Semiconductors – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. ...
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... NXP Semiconductors • Supports DMA transfers with the DMA RAM all non-control endpoints. • Allows dynamic switching between CPU-controlled and DMA modes. • Double buffer implementation for Bulk and Isochronous endpoints. 7.10.2 USB host controller The host controller enables full- and low-speed data exchange with USB devices attached to the bus ...
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... NXP Semiconductors 7.11.1 Features • Two CAN controllers and buses. • Data rates to 1 Mbit/s on each bus. • 32-bit register and RAM access. • Compatible with CAN specification 2.0B, ISO 11898-1. • Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN buses. • ...
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... NXP Semiconductors 7.14.1 Features • Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. ...
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... NXP Semiconductors 7.17 SD/MMC card interface The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD memory cards. The SD card interface conforms to the SD Multimedia Card Specification Version 2.11. 7.17.1 Features • The MCI provides all functions specific to the SD/MMC memory card. These include the clock generation unit, power management control, and command and data transfer ...
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... NXP Semiconductors 2 7.19 I S-bus serial I/O controllers 2 The I S-bus provides a standard communication interface for digital audio applications. 2 S-bus specification defines a 3-wire serial bus using one data line, one clock line, The I and one word select signal. The basic I master, and one slave. The I and receive channel, each of which can operate as either a master or a slave ...
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... NXP Semiconductors – Do nothing on match. 7.21 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2387. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers ...
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... NXP Semiconductors • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • ...
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... NXP Semiconductors • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Dedicated 32 kHz oscillator or programmable prescaler from APB clock. • Dedicated power supply pin can be connected to a battery or to the main 3.3 V. • Periodic interrupts can be generated from increments of any field of the time registers, and selected fractional second values. • ...
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... NXP Semiconductors The PLL input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value ‘N’, which may be in the range 256. This input division provides a wide range of output frequencies from the same input frequency. Following the PLL input divider is the PLL multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO value ‘ ...
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... NXP Semiconductors The LPC2387 also implements a separate power domain in order to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small SRAM, referred to as the battery RAM. 7.24.4.1 Idle mode In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs ...
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... NXP Semiconductors If power is supplied to the LPC2387 during Deep power-down mode, wake-up can be caused by the RTC Alarm interrupt or by external Reset. While in Deep power-down mode, external device power may be removed. In this case, the LPC2387 will start up when external power is restored. Essential data may be retained through Deep power-down mode (or through complete powering off of the chip) by storing data in the Battery RAM, as long as the external power to the VBAT pin is maintained ...
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... NXP Semiconductors 7.25.2 Brownout detection The LPC2387 includes 2-stage monitoring of the voltage on the V voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register ...
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... NXP Semiconductors The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB bus master on AHB1, allowing expansion of Ethernet buffer space into unused space in memory residing on AHB1. ...
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... NXP Semiconductors information about processor execution to a trace port. A software debugger allows configuration of the ETM using a JTAG interface and displays the trace information that has been captured. The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port ...
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... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter supply voltage DD(DCDC)(3V3) (3 analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V input voltage on pin VREF ...
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... NXP Semiconductors 9. Thermal characteristics The average chip junction temperature, T equation amb • T amb • R th(j-a) • The internal power dissipation is the product of I the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 5. Thermal characteristics ...
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... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter DD(DCDC)(3V3) supply voltage (3 analog 3.3 V pad supply DDA voltage V input voltage on pin i(VBAT) VBAT ...
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... NXP Semiconductors Table 7. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter I I/O latch-up current latch V input voltage I V output voltage O V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys V HIGH-level output ...
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... NXP Semiconductors Table 7. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter USB pins I OFF-state output OZ current V bus supply voltage BUS V differential input DI sensitivity voltage V differential common CM mode voltage range V single-ended receiver th(rs)se switching threshold ...
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... NXP Semiconductors 10.1 Power-down mode I DD(IO) (μA) Fig 4. I (μA) Fig 5. LPC2387 Product data sheet −2 −4 −40 − 3 i(VBAT) DD(DCDC)(3V3) amb I/O maximum supply current I 40 BAT 3.3 V i(VBAT 3.0 V i(VBAT −40 − 3 DD(3V3) DD(DCDC)(3V3) ...
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... NXP Semiconductors I DD(DCDC)pd(3v3) Fig 6. 10.2 Deep power-down mode I DD(IO) (μA) Fig 7. LPC2387 Product data sheet 800 (μA) 600 400 V = 3.3 V DD(DCDC)(3V3) 200 V = 3.0 V DD(DCDC)(3V3) 0 −40 − 3 DD(3V3) i(VBAT) amb Total DC-to-DC converter supply current I in Power-down mode ...
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... NXP Semiconductors I (μA) Fig 8. I DD(DCDC)dpd(3v3) Fig 9. LPC2387 Product data sheet 40 BAT 3.3 V i(VBAT 3.0 V i(VBAT −40 − 3 DD(3V3) DD(DCDC)(3V3) RTC battery maximum supply current I power-down mode 100 (μ 3.3 V DD(DCDC)(3V3 3.0 V DD(DCDC)(3V3 −40 − ...
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... NXP Semiconductors 10.3 Electrical pin characteristics V Fig 10. Typical HIGH-level output voltage V (mA) Fig 11. Typical LOW-level output current I LPC2387 Product data sheet 3 °C 25 °C 3.2 −40 °C 2.8 2.4 2 Conditions 3.3 V; standard port pins. DD(3V3 0.2 Conditions 3.3 V; standard port pins. ...
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... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics +85 C for commercial applications; V amb Symbol Parameter External clock (see Figure 12) f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t clock LOW time CLCX t clock rise time ...
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... NXP Semiconductors 11.1 Internal oscillators Table 9. Dynamic characteristic: internal oscillators +85 C; 3.0 V amb Symbol Parameter f internal RC oscillator frequency osc(RC) f RTC input frequency i(RTC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. ...
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... NXP Semiconductors 11.4 Flash memory Table 12. Dynamic characteristics of flash +85 C, unless otherwise specified; V amb ground. Symbol Parameter N endurance endu t retention time ret t erase time er t programming time prog [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. ...
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... NXP Semiconductors 11.5 Timing T PERIOD differential data lines Fig 13. Differential data-to-EOP transition skew and EOP width shifting edges SCK MOSI MISO Fig 14. MISO line set-up time in SSP Master mode LPC2387 Product data sheet crossover point crossover point differential data to SE0/EOP skew n × ...
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... NXP Semiconductors 12. ADC electrical characteristics Table 13. ADC electrical characteristics 2 3 DDA amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G E absolute error T R voltage source interface ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. ...
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... NXP Semiconductors AD0[y] Fig 16. Suggested ADC interface - LPC2387 AD0[y] pin LPC2387 Product data sheet LPC23XX 20 kΩ SAMPLE All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 January 2012 LPC2387 Single-chip 16-bit/32-bit MCU R vsi AD0[y] V EXT 002aac610 © ...
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... NXP Semiconductors 13. DAC electrical characteristics Table 14. DAC electrical characteristics 3 3 DDA amb Symbol Parameter E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G C load capacitance L R load resistance L LPC2387 Product data sheet ...
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... NXP Semiconductors 14. Application information 14.1 Suggested USB interface solutions LPC23XX Fig 17. LPC2387 USB interface on a self-powered device LPC23XX Fig 18. LPC2387 USB interface on a bus-powered device LPC2387 Product data sheet V DD(3V3) USB_UP_LED USB_CONNECT SoftConnect switch R1 1.5 kΩ V BUS Ω USB_D Ω ...
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... NXP Semiconductors RSTOUT LPC2387 USB_SCL1 USB_SDA1 EINTn USB_D+ USB_D- Fig 19. LPC2387 USB OTG port configuration USB_UP_LED USB_D+ USB_D− LPC2387 USB_PWRD1 USB_OVRCR1 USB_PPWR1 Fig 20. LPC2387 USB host port configuration LPC2387 Product data sheet RESET_N ADR/PSW OE_N/INT_N V DD SPEED ...
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... NXP Semiconductors USB_UP_LED USB_CONNECT LPC2387 USB_D+ USB_D− V BUS Fig 21. LPC2387 USB device port configuration 14.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF ...
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... NXP Semiconductors Fig 23. Oscillator modes and models: oscillation mode of operation and external crystal Table 15. Fundamental oscillation frequency F 1 MHz to 5 MHz 5 MHz to 10 MHz 10 MHz to 15 MHz 15 MHz to 20 MHz Table 16. Fundamental oscillation frequency F 15 MHz to 20 MHz 20 MHz to 25 MHz ...
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... NXP Semiconductors 14.3 RTC 32 kHz oscillator component selection Fig 24. RTC oscillator modes and models: oscillation mode of operation and external The RTC external oscillator circuit is shown in integrated on chip, only a crystal, the capacitances C externally to the microcontroller. Table 17 capacitance of the crystal and is usually specified by the crystal manufacturer. The actual C influences oscillation frequency ...
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... NXP Semiconductors 14.5 Standard I/O pin configuration Figure 25 • Digital output driver • Digital input: Pull-up enabled/disabled • Digital input: Pull-down enabled/disabled • Analog input (for ADC input channels) The default configuration for standard I/O pins is input with pull-up enabled. The weak MOS devices provide a drive capability equivalent to pull-up and pull-down resistors. ...
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... NXP Semiconductors 14.6 Reset pin configuration Fig 26. Reset pin configuration LPC2387 Product data sheet reset GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 January 2012 LPC2387 Single-chip 16-bit/32-bit MCU ESD ESD V SS 002aaf274 © ...
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... NXP Semiconductors 15. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 1 pin 1 index 100 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Abbreviations Table 18. Acronym ADC AHB AMBA APB BOD CAN DAC DCC DMA DSP EOP ETM GP GPIO IrDA JTAG MII MIIM PHY PLL PWM RMII SE0 SPI SSI SSP TTL UART USB LPC2387 Product data sheet Abbreviations Description Analog-to-Digital Converter ...
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... NXP Semiconductors 17. Revision history Table 19. Revision history Document ID Release date LPC2387 v.5 20120109 • Modifications: Table 3 “Pin pull-down resistor.” • Table 3 “Pin TMS, TDI, TRST, and RTCK pins. • Table 3 “Pin • Added • Table 4 “Limiting • Table 4 “Limiting temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime ...
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... NXP Semiconductors Table 19. Revision history …continued Document ID Release date LPC2387 v.4 20110210 • Modifications: Table 3 “Pin description”: Added Table note 9 for XTAL1 and XTAL2 pins. • Table 3 “Pin description”: Added Table note 10 for RTCX1 and RTCX2 pins. • Table 4 “Limiting values”: Changed V • ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . 14 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 14 7.2 On-chip flash programming memory . . . . . . . 15 7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 Memory map 7.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 16 7.5.1 Interrupt sources ...
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... NXP Semiconductors 18 Legal information 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 63 18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 18.4 Trademarks Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Single-chip 16-bit/32-bit MCU Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. ...