80C31_80C32 NXP Semiconductors, 80C31_80C32 Datasheet - Page 23

• Manufacturer Part Number: 80C31_80C32
• Description: The Philips 80C31/32 is a high-performance static 80C51 designfabricated with Philips high-density CMOS technology with operationfrom 2
• Manufacturer: NXP Semiconductors

1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the 80C31 and 80C32 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to
4. See application note AN457 for external memory interface.
5. Parts are guaranteed to operate down to 0 Hz. When an external clock source is used, the RST pin should be held high for a minimum of
Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS
T
NOTES:
2000 Aug 07
amb
1/t
t
t
t
t
t
t
t
t
t
t
t
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
External Clock
t
t
t
t
Shift Register
t
t
t
t
t
SYMBOL
LHLL
AVLL
LLAX
LLIV
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
WHQX
QVWH
RLAZ
WHLH
CHCX
CLCX
CLCH
CHCL
XLXL
QVXH
XHQX
XHDX
XHDV
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
Port 0 drivers.
20 s for power-on or wakeup from power down.
CLCL
= 0 C to +70 C or –40 C to +85 C, V
4
FIGURE
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
14
14
14
14
14
14
14
14
14
14
14
14
16
18
18
18
18
17
17
17
17
17
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
High time
Low time
Rise time
Fall time
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
Speed versions :S
CC
PARAMETER
= +2.7 V to +5.5 V, V
5
SS
= 0 V
23
1, 2, 3
16 MHz CLOCK
MIN
142
275
275
137
122
287
750
492
85
22
32
32
13
13
23
20
20
0
0
8
0
MAX
150
207
147
350
397
239
103
492
82
37
10
65
20
20
0
10t
6t
6t
4t
7t
2t
2t
3t
3t
t
t
t
t
t
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
12t
CLCL
CLCL
CLCL
CLCL
CLCL
MIN
3.5
20
20
CLCL
VARIABLE CLOCK
0
0
0
–40
–30
–30
–100
–100
–130
–50
–50
–150
–40
–117
–40
–45
–50
–133
80C31/80C32
10t
t
t
4t
3t
5t
5t
8t
9t
CLCL
CLCL
2t
3t
t
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
MAX
16
10
20
20
–t
–t
0
Product specification
–100
–105
–25
–105
–165
–150
–165
+40
CHCX
CLCX
–60
+50
–133
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns