JN5148 NXP Semiconductors, JN5148 Datasheet
JN5148
Available stocks
Related parts for JN5148
JN5148 Summary of contents
Page 1
... Data Sheet: JN5148-001 IEEE802.15.4 Wireless Microcontroller Overview The JN5148-001 is an ultra low power, high performance wireless microcontroller targeted at JenNet applications. The device features an enhanced 32-bit RISC processor offering high coding efficiency through variable width instructions, a multi- stage instruction pipeline and low power operation with programmable clock speeds ...
Page 2
... Crystal Oscillator 5.2.3 32kHz External Clock 6 Reset 6.1 Internal Power-on Reset 6.2 External Reset 6.3 Software Reset 6.4 Brown-out Detect 6.5 Watchdog Timer 7 Interrupt System 7.1 System Calls 7.2 Processor Exceptions 7.2.1 Bus Error 7.2.2 Alignment 7.2.3 Illegal Instruction 7.2.4 Stack Overflow 7.3 Hardware Interrupts 2 JN-DS-JN5148-001 1v7 ...
Page 3
... Master Two-wire Serial Interface 15.4 Slave Two-wire Serial Interface 16 Four-Wire Digital Audio Interface 17 Random Number Generator 18 Sample FIFO 19 Intelligent Peripheral Interface 19.1 Data Transfer Format 19.2 JN5148 (Slave) Initiated Data Transfer 19.3 Remote (Master) Processor Initiated Data Transfer © NXP Laboratories UK 2011 JN-DS-JN5148-001 1v7 ...
Page 4
... Crystal Oscillator 22.3.14 24MHz RC Oscillator 22.3.15 Temperature Sensor 22.3.16 Radio Transceiver Appendix A Mechanical and Ordering Information A.1 56-pin QFN Package Drawing A.2 PCB Decal A.3 Ordering Information A.4 Device Package Marking A.5 Tape and Reel Information A.5.1 Tape Orientation and Dimensions 4 JN-DS-JN5148-001 1v7 ...
Page 5
... A.5.4 Dry Pack Requirement for Moisture Sensitive Material Appendix B Development Support B.1 Crystal Oscillators B.1.1 Crystal Equivalent Circuit B.1.2 Crystal Load Capacitance B.1.3 Crystal ESR and Required Transconductance B.2 32MHz Oscillator B.3 32kHz Oscillator B.4 JN5148 Module Reference Designs B.4.1 Schematic Diagram B.4.2 PCB Design and Reflow Profile Related Documents RoHS Compliance Status Information Disclaimers Version Control Contact Details © ...
Page 6
... A 32-bit RISC CPU allows software to be run on chip, its processing power being shared between the IEEE802.15.4 MAC protocol, other higher layer protocols and the user application. The JN5148 has a unified memory architecture, code memory, data memory, peripheral devices and I/O ports are organised within the same linear address space. ...
Page 7
... JTAG hardware debug port User applications access the peripherals using the Integrated Peripherals API. This allows applications to use a tested and easily understood view of the peripherals allowing rapid system development. © NXP Laboratories UK 2011 2 C) supporting master and slave operation JN-DS-JN5148-001 1v7 7 ...
Page 8
... Sample I2S_CLK Audio FIFO I2S_SYNC Interf ace Wireless Transceiv er Security Coprocessor T ime Digital Of Baseband Flight Radio Figure 1: JN5148 Block Diagram JN-DS-JN5148-001 1v7 SPICLK SPIMOSI SPIMISO SPISEL0 DIO0/SPISEL1 DIO1/SPISEL2/PC0 DIO2/SPISEL3/RFRX DIO3/SPISEL4/RFTX DIO4/CTS0/JT AG_T CK DIO5/RTS0/JT AG_T MS DIO6/TXD0/JTAG_TDO DIO7/RXD0/JTAG_T DI DIO8/T IM0CK_G T /PC1 DIO9/T IM0CAP/32KXTALIN/32KIN ...
Page 9
... VCOTUNE 11 VB_VCO 12 VDD1 13 IBIAS 14 Figure 2: 56-pin QFN Configuration (top view) Note: Please refer to Appendix B.4 JN5148 Module Reference Design for important applications information regarding the connection of the PADDLE to the PCB. © NXP Laboratories UK 2011 VSSA (Paddl e) JN-DS-JN5148-001 1v7 DIO2/SPISEL3/RFRX 42 41 DIO1/SPISEL2/PC0 ...
Page 10
... SPISEL3 RFRX SPISEL4 RFTX CTS0 JTAG_TCK RTS0 JTAG_TMS TXD0 JTAG_TDO RXD0 JTAG_TDI PC1 TIM0CAP 32KXTALIN 32KIN JN-DS-JN5148-001 1v7 Signal Description Type 1.8V Regulated supply voltage 3.3V Supplies: VDD1 for analogue, VDD2 for digital 0V Grounds (see appendix A.2 for paddle details) No connect CMOS Reset input 1.8V System crystal oscillator 1 ...
Page 11
... RXD1 The PCB schematic and layout rules detailed in Appendix B.4 must be followed. Failure will likely result in the JN5148 failing to meet the performance specification detailed herein and worst case may result in device not functioning in the end application. © NXP Laboratories UK 2011 ...
Page 12
... RESETN is a bi-directional active low reset pin that is connected to a 40kΩ internal pull-up resistor. It may be pulled low by an external circuit, or can be driven low by the JN5148 if an internal reset is generated. Typically, it will be used to provide a system reset signal. Refer to section 6.2, External Reset, for more details. ...
Page 13
... There are four ADC inputs, two pairs of comparator inputs and two DAC outputs. The analogue I/O pins on the JN5148 can have signals applied up to 0.3v higher than VDD1. A schematic view of the analogue I/O cell is shown in Figure 3: Analogue I/O Cell In reset and deep sleep, the analogue peripherals are all off and the DAC outputs are in a high impedance state ...
Page 14
... In reset, the digital peripherals are all off and the DIO pins are set as high-impedance inputs. During sleep and deep sleep, the DIO pins retain both their input/output state and output level that was set as sleep commences. If the DIO pins were enabled as inputs and the interrupts were enabled then these pins may be used to wake up the JN5148 from sleep. ...
Page 15
... GP registers to contain the address of objects. Subroutine parameter passing is also made more efficient by using GP registers rather than pushing objects onto the stack. The recommended programming method for the JN5148 is by using C, which is supported by a software developer kit comprising a C compiler, linker and debugger. ...
Page 16
... Memory Organisation This section describes the different memories found within the JN5148. The device contains ROM, RAM, OTP eFuse memory, the wireless transceiver and peripherals all within the same linear address space. 4.1 ROM The ROM is 128k bytes in size, and can be accessed by the processor in a single CPU clock cycle. The ROM contents include bootloader to allow external Flash memory contents to be bootloaded into RAM at runtime, a default interrupt vector table, an interrupt manager, IEEE802 ...
Page 17
... RAM The JN5148 contains 128kBytes of high speed RAM. It can be used for both code and data storage and is accessed by the CPU in a single clock cycle. At reset, a boot loader controls the loading of segments of code and data from an external memory connected to the SPI port, into RAM. Software can control the power supply to the RAM allowing the contents to be maintained during a sleep period when other parts of the device are un-powered ...
Page 18
... At reset, the contents of this memory are copied into RAM by the software boot loader. The Flash memory devices that are supported as standard through the JN5148 bootloader are given in Table 1. Jennic recommends that where possible one of these devices should be selected. Manufacturer SST (Silicon Storage Technology) ...
Page 19
... System Clocks Two system clocks are used to provide timing references into the on-chip subsystems of the JN5148. A 16MHz clock, generated by a crystal-controlled 32MHz oscillator, is used by the transceiver, processor, memory and digital and analogue peripherals. A 32kHz clock is used by the sleep timer and during the startup phase of the chip. ...
Page 20
... Crystal Oscillator • 32kHz External Clock Upon a chip reset or power-up the JN5148 defaults to using the internal 32kHz RC Oscillator. If another clock source is selected then it will remain in use for all 32kHz timing until a chip reset is performed. 5.2.1 32kHz RC Oscillator The internal 32kHz RC oscillator requires no external components. The internal timing components of the oscillator have a wide tolerance due to manufacturing process variation and so the oscillator runs nominally at 32kHz ± ...
Page 21
... A system reset initialises the device to a pre-defined state and forces the CPU to start program execution from the reset vector. The reset process that the JN5148 goes through is as follows. When power is applied, the 32kHz RC oscillator starts up and stabilises, which takes approximately 100µsec. At this point, the 32MHz crystal oscillator is enabled and power is applied to the processor and peripheral logic ...
Page 22
... RESETN pin is driven low for 1µsec; depending on the external components this may or may not be visible on the pin. In addition, the RESETN line can be driven low by the JN5148 to provide a reset to other devices in the system (e.g. external sensors) without resetting itself. When the RESETN line is not driven it will pull back high through either the internal pull-up resistor or any external circuitry essential to ensure that the RESETN line pulls back high within 100µ ...
Page 23
... CPU doze mode. Dips in the supply voltage below a variable threshold can be detected and can be used to cause the JN5148 to perform a chip reset. Equally, dips in the supply voltage can be detected and used to cause an interrupt to the processor, when the voltage either drops below the threshold or rises above it. ...
Page 24
... Interrupt System The interrupt system on the JN5148 is a hardware-vectored interrupt system. The JN5148 provides several interrupt sources, some associated with CPU operations (CPU exceptions) and others which are used by hardware in the device. When an interrupt occurs, the CPU stops executing the current program and loads its program counter with a fixed hardware address specific to that interrupt ...
Page 25
... For details of the interrupts generated from each peripheral see the respective section in this datasheet. Interrupts can be used to wake the JN5148 from sleep. The peripherals, baseband controller, security coprocessor and PIC are powered down during sleep but the DIO interrupts and optionally the pulse counters, wake-up timers and analogue comparator interrupts remain powered to bring the JN5148 out of sleep ...
Page 26
... The 2.4 GHz signal from the VCO is then passed to the RF Power Amplifier (PA), whose power control can be selected from one of three settings. The output of the PA drives the antenna via the RX/TX switch 26 Calibration Reference & Bias synth Figure 14: Radio Architecture JN-DS-JN5148-001 1v7 Radio ADC sigma delta © NXP Laboratories UK 2011 ...
Page 27
... The RF matching network requires three external components and the IBIAS pin requires one external component as shown in schematic in B.4.1. These components are critical and should be placed close to the JN5148 pins and analogue ground as defined in Table 8: JN5148 Printed Antenna Reference Module Components and PCB Layout Constraints ...
Page 28
... If two DIO pins cannot be spared, DIO13 can be configured normal DIO pin, and the inverse of ADO generated with an inverter on the PCB. 28 Antenna Switch: Single-Pole, Double-Throw (SPDT) COM Device RF Port 1st TX-RX Cycle 2nd TX-RX Cycle (1st Retry) JN-DS-JN5148-001 1v7 © NXP Laboratories UK 2011 ...
Page 29
... The CCA capability of the Modem supports all modes of operation defined in the IEEE 802.15.4 standard, namely Energy above ED threshold, Carrier Sense and Carrier Sense and/or energy above ED threshold. Figure 19 Energy Detect Value vs Receive Power Level © NXP Laboratories UK 2011 RX Symbol Demodulation Detection (Despreading) TX Spreading Figure 18 Modem Architecture JN-DS-JN5148-001 1v7 RX Data Interface TX Data Interface 29 ...
Page 30
... An interrupt may be 30 Security Coprocessor Encrypt Port AES Codec Decrypt Port Figure 20: Baseband Processor JN-DS-JN5148-001 1v7 Tx/Rx Frame Buffer Protocol Timers Processor Bus © NXP Laboratories UK 2011 ...
Page 31
... Figure 21: Security Coprocessor Architecture 8.5 Location Awareness The JN5148 provides the ability for an application to obtain the Time Of Flight (TOF) between two network nodes. The TOF information is an alternative metric to that of the existing Energy Detect value (RSSI) that has been typically used for calculating the relative inter-nodal separation, for subsequent use in a location awareness system. ...
Page 32
... IEEE802.15.4 features, such as clear channel assessment, can still be used. This allows the JN5148 in a higher data rate mode to co-exist in an IEEE802.15.4 based network (adhering to the correct bit rates and frame timing etc.) whilst at the same time providing the benefit of the higher data rate where required. ...
Page 33
... Two DIO pins can optionally be used to provide control signals for RF circuitry (eg switches and PA) in high power range extenders. DIO3 / RFTX is asserted when the radio is in the transmit state and similarly, DIO2 / RFRX is asserted when the radio is in the receiver state. © NXP Laboratories UK 2011 JN-DS-JN5148-001 1v7 33 ...
Page 34
... I2S_CLK Interface I2S_SYNC 34 SPICLK SPIMOSI SPIMISO SPISEL0 DIO0/SPISEL1 DIO1/SPISEL2/PC0 DIO2/SPISEL3/RFRX DIO3/SPISEL4/RFTX DIO4/CTS0/JTAG_TCK DIO5/RTS0/JTAG_TMS DIO6/TXD0/JTAG_TDO DIO7/RXD0/JTAG_TDI DIO8/TIM0CK_GT/PC1 DIO9/TIM0CAP/32KXTALIN/32KIN DIO10/TIM0OUT/32KXTALOUT DIO11/TIM1CK_GT/TIM2OUT DIO12/TIM1CAP/ADO/DAI_WS DIO13/TIM1OUT/ADE/DAI_SDN DIO14/SIF_CLK/IP_CLK DIO15/SIF_D/IP_DO DIO16/IP_DI MUX DIO17/CTS1/IP_SEL/DAI_SCK/ JTAG_TCK DIO18/RTS1/IP_INT/DAI_SDOUT/ JTAG_TMS DIO19/TXD1/JTAG_TDO DIO20/RXD1/JTAG_TDI Figure 22 DIO Block Diagram JN-DS-JN5148-001 1v7 © NXP Laboratories UK 2011 ...
Page 35
... The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the JN5148 and peripheral devices. The JN5148 operates as a master on the SPI bus and all other devices connected to the SPI are expected to be slave devices under the control of the JN5148 CPU. The SPI includes the following features: • ...
Page 36
... Both SPICLK clock phase and polarity are configurable. The clock phase determines which edge of SPICLK is used by the JN5148 to present new data on the SPIMOSI line; the opposite edge will be used to read data from the SPIMISO line. The interface should be configured appropriately for the SPI slave being accessed ...
Page 37
... An interrupt can be generated when the transaction has completed or alternatively the interface can be polled slave device wishes to signal the JN5148 indicating that it has data to provide, it may be connected to one of the DIO pins that can be enabled as an interrupt. ...
Page 38
... Int Enable INT Interrupt Generator Rise = Fall = PWM/∆−Σ Counter PWM/∆−Σ Reset System Single Reset Shot Figure 26: Timer Unit Block Diagram JN-DS-JN5148-001 1v7 OE S TIMxOUT R PWM/Delta- Sigma © NXP Laboratories UK 2011 ...
Page 39
... Therefore, if multiple pulses are seen on TIMxCAP before the counter is stopped only the last pulse width will be stored. © NXP Laboratories UK 2011 prescale value. For example, a prescale value of Rise Fall Figure 27: PWM Output Timings JN-DS-JN5148-001 1v7 39 ...
Page 40
... RTZ and NRZ for the same programmed number of pulses RISE RISE Capture Mode Enabled 9 x Figure 28: Capture Mode 17 clocks. The integrated output will only reach half VDD2 in RTZ mode, JN-DS-JN5148-001 1v7 4 t FALL © NXP Laboratories UK 2011 ...
Page 41
... Figure 31: Closed Loop PWM Speed Control Using JN5148 Timers 11.2 Tick Timer The JN5148 contains a hardware timer that can be used for generating timing interrupts to software. It may be used to implement regular events such as ticks for software timers or an operating system high-precision timing reference or can be used to implement system monitor timeouts as used in a watchdog timer. Features include: • ...
Page 42
... An interrupt will be generated when the match value is reached if enabled. 11.3 Wakeup Timers Two 32-bit wakeup timers are available in the JN5148 driven from the 32kHz internal clock. They may run during sleep periods when the majority of the rest of the device is powered down, to time sleep periods or other long period timings that may be required by the application ...
Page 43
... RC clock and the 16MHz system clock when the JN5148 is awake. Wakeup timer0 counts for a set number of 32kHz clock periods during which time the reference counter runs. When the wakeup timer reaches zero the reference counter is stopped, allowing software to read the number of 16MHz clock ticks generated during the time represented by the number of 32kHz ticks programmed in the wakeup timer ...
Page 44
... The system can work with signals up to 100kHz, with no debounce, or from 5.3kHz to 1.7kHz with debounce. When using debounce the 32kHz clock must be active, so for minimum sleep currents the debounce mode should not be used. 44 JN-DS-JN5148-001 1v7 © NXP Laboratories UK 2011 ...
Page 45
... Serial Communications The JN5148 has two independent Universal Asynchronous Receiver/Transmitter (UART) serial communication interfaces. These provide similar operating features to the industry standard 16550A device operating in FIFO mode. Each interface performs serial-to-parallel conversion on incoming serial data and parallel-to-serial conversion on outgoing data from the CPU to external devices. In both directions, a 16-byte deep FIFO buffer allows the CPU to read and write multiple characters on each transaction ...
Page 46
... Modem Status: Generated when the CTS (Clear To Send) input control line changes. 13.2 UART Application The following example shows the UART connected to a 9-pin connector compatible with a PC. As the JN5148 device pins do not provide the RS232 line voltage, a level shifter is used. JN5148 ...
Page 47
... It is possible to prevent all hardware debugging by blowing the relevant Efuse bit. The JTAG interface does not support boundary scan testing recommended that the JN5148 is not connected as part of the board scan chain. © NXP Laboratories UK 2011 ...
Page 48
... Two-Wire Serial Interface The JN5148 includes industry standard two-wire synchronous Serial Interface operates as a Master (MSIF) or Slave (SSIF) that provides a simple and efficient method of data exchange between devices. The system uses a serial data line (SIF_D) and a serial clock line (SIF_CLK) to perform bi-directional data transfers and includes the following ...
Page 49
... The first byte of data transferred by the device after a start bit is the slave address. The JN5148 supports both 7-bit and 10-bit slave addresses by generating either one or two address transfers. Only the slave with a matching address will respond by returning an acknowledge bit ...
Page 50
... A protocol error has been spotted on the interface 50 Name General Call/Start Byte CBUS address Reserved Reserved Hs-mode master code Reserved 10-bit address JN-DS-JN5148-001 1v7 Behaviour Ignored Ignored Ignored Ignored Ignored Ignored Only responded bit address set in address register © NXP Laboratories UK 2011 ...
Page 51
... Four-Wire Digital Audio Interface The JN5148 includes a four-wire digital audio interface that can be used for interfacing to audio CODECs. The following features are supported: • Compatible with the industry standard I²S interface • Option to support I²S, left justified and right justified modes • ...
Page 52
... MSB MSB Figure 39: Left Justified Mode Right Left Left LSB MSB MSB Figure 40: Right Justified Mode JN-DS-JN5148-001 1v7 Right MSB-1 MSB-2 LSB Right MSB-2 LSB Right LSB © NXP Laboratories UK 2011 ...
Page 53
... In either mode of operation an interrupt can be generated to indicate when the number is available status bit can be polled. The random bits are generated by sampling the state of the 32MHz clock every 32kHz system clock edge. As these clocks are asynchronous to each other, each sampled bit is unpredictable and hence random. © NXP Laboratories UK 2011 JN-DS-JN5148-001 1v7 53 ...
Page 54
... PWM output with a rising edge generated every time a digital audio transfer is required. The transfer rate is typically configured to be the audio sample rate, e.g. 8kHz. If the transfer rate is too fast or slow data will be transferred correctly between the FIFO and the digital audio block. 54 JN-DS-JN5148-001 1v7 © NXP Laboratories UK 2011 ...
Page 55
... The first byte transferred into the JN5148 is a status byte with the format shown in Table 6. This is followed by a padding byte that should be set to zero. The first byte output by the JN5148 is a padding byte, that should be ignored, followed by a status byte with the format shown in Table 6 ...
Page 56
... If data is queued for transmission and the recipient has indicated that they are ready for it (RXRDY in incoming status byte was 1), the next byte to be transmitted is the data length in words (N). If either the JN5148 or the remote processor has no data to transfer, then the data length should be set to zero. The transaction can be terminated by the master after the status and padding bytes have been sent not possible to send data in either direction ...
Page 57
... IP_DI with RXRDY set. After receiving the status byte from the JN5148, it should check that the JN5148 has a buffer ready by reading the TXRDY bit of the received status byte. If the TXRDY bit is 0, indicating that the JN5148 does not have data to send, it must terminate the transfer by deasserting IP_SEL unless it is transmitting data to the JN5148 ...
Page 58
... Analogue Peripherals The JN5148 contains a number of analogue peripherals allowing the direct connection of a wide range of external sensors, switches and actuators. Chip Boundary VREF ADC1 ADC2 ADC3 ADC4 Temp Sensor COMP1P COMP1M COMP2P COMP2M DAC1 DAC2 In order to provide good isolation from digital noise, the analogue peripherals are powered by a separate regulator, supplied from the analogue supply VDD1 and referenced to analogue ground VSSA ...
Page 59
... The end of conversion © NXP Laboratories UK 2011 Maximum Input Range Supply Voltage Range (VDD) 1.2V 1.6V 2.4V 3.2V Sample Switch 5 K ADC 8 pF Figure 44 ADC Input Equivalent Circuit JN-DS-JN5148-001 1v7 2.2V - 3.6V 2.2V - 3.6V 2.6V - 3.6V 3.4V - 3.6V front end 59 ...
Page 60
... Simultaneous conversions with DAC1 and DAC2 are possible. To use both DACs at the same time it is only necessary to enable them and supply the digital values via the software. The DACs should not be used in single shot mode, but continuous conversion mode only, in order to maintain a steady output voltage. 60 JN-DS-JN5148-001 1v7 © NXP Laboratories UK 2011 ...
Page 61
... This mode may be used during non-sleep operation however it is particularly useful in sleep mode to wake up the JN5148 from sleep where low current consumption is important. The wakeup action and the configuration for which edge of the comparator output will be active are controlled through software. In sleep mode the negative input signal source, must be configured to be driven from the external pins. © ...
Page 62
... The current consumption figures for the different modes of operation of the device is given in section 22.2.2. 21.2 Active Processing Mode Active processing mode in the JN5148 is where all of the application processing takes place. By default, the CPU will execute at the selected clock speed executing application firmware. All of the peripherals are available to the application, as are options to actively enable or disable them to control power consumption ...
Page 63
... Pulse Counter The JN5148 contains two 16 bit pulse counters that can be programmed to generate a wake-up event. Following the wakeup event the counters will continue to operate and therefore no pulse will be missed during the wake-up process. These counters are described in section 12. ...
Page 64
... Testing for Charged Device Model discharge is performed as specified in JEDEC Standard JESD22-C101. 22.2 DC Electrical Characteristics 22.2.1 Operating Conditions Supply VDD1, VDD2 Ambient temperature range 64 Min -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -40º Min 2.0V -40ºC JN-DS-JN5148-001 1v7 Max 3.6V 1.98V VB_xxx + 0.3V VDD1 + 0.3V Lower of (VDD2 + 2V) and 5.5V VDD2 + 0.3V 150ºC 260ºC 2.0kV 500V Max 3.6V 85ºC © NXP Laboratories UK 2011 ...
Page 65
... Typ Max Unit 100 nA JN-DS-JN5148-001 1v7 Notes SPI, GPIOs enabled. When in CPU doze the current related to CPU speed is not consumed. CPU in software doze – radio transmitting CPU in software doze – radio in receive mode Temperature sensor and battery measurements require ADC ...
Page 66
... VDD2 VDD2 x 0.27 230 310 VDD2 0.4 VDD2 0.4 VDD2 0 2 POT t STAB JN-DS-JN5148-001 1v7 Unit Notes VDD2 = 3.6V, 25C kΩ VDD2 = 3.0V, 25C VDD2 = 2.2V, 25C VDD2 = 2.0V, 25C V 5V Tolerant I/O only With 4mA load V With 4mA load V With 3mA load V With 3mA load V With 2 ...
Page 67
... STAB Figure 46: Externally Applied Reset Typ Max 1.47 1.42 0.84 1.95 2.01 2.25 2.32 2.65 2.73 2.95 3. 100 DVDD JN-DS-JN5148-001 1v7 Unit Notes Assumes internal pullup µs resistor value of 100K worst case and ~5pF external capacitance V Minimum voltage to avoid being reset V Rising Falling ms Note 1 V Configurable threshold with 4 levels mV Corresponding to the 4 ...
Page 68
... Figure 49: Intelligent Peripheral (SPI Slave) Timing Figure 48: SPI Timing (Master) Min 62.5 16.7 @ 3.3V 18.2 @ 2.7V 21 (SPICLK = 16MHz) 0 (SPICLK<16MHz, mode (SPICLK<16MHz, mode JN-DS-JN5148-001 1v7 t SSH Max Unit - ssh t hz © NXP Laboratories UK 2011 ...
Page 69
... HD:STA t 4.7 LOW t 4 HIGH t 4.7 SU:STA t 0.25 SU:DAT t - 1000 300 SU:STO t 4.7 BUF 400 b V 0.1VDD nl V 0.2VDD nh JN-DS-JN5148-001 1v7 Max Unit - BUF t SU;STO P S Fast Mode Unit Min Max 0 400 kHz - 0.6 - µ ...
Page 70
... Typ Max Unit 0.84 ms 1.0 ms 0.84 + 0.5* ms program size in kBytes 0.84 ms 0.2 µs 0.29 ms JN-DS-JN5148-001 1v7 Generic Unit Min Max 125 - Notes Reached oscillator amplitude threshold Assumes SPI clock to external Flash is 16MHz ...
Page 71
... Typ Max 12 655 ± 500 Vref or 2*Vref See Section 22.3.7 Bandgap Reference 1.2 1.6 8 JN-DS-JN5148-001 1v7 Unit Notes 25ºC ppm/º 85ºC -40ºC to 20ºC ºC Unit Notes bits 500kHz Clock µA LSB 0 to Vref range LSB ...
Page 72
... Lower of Vdd-1.2 and Vref 0 Lower of 2x(Vdd-1.2 ) and Vdd-0.2 and 2xVref See Section 22.3.7 Bandgap Reference 1.2 1 Binary JN-DS-JN5148-001 1v7 Unit Notes bits µA LSB LSB Guaranteed monotonic mV mV 16MHz input clock, programmable prescaler µs With 10k ohms & 20pF load µ ...
Page 73
... Vdd 54 73 102 0.8 Typ Max 1.45 1.25 1.05 32kHz +30% ±250 -0.010 -1.1 JN-DS-JN5148-001 1v7 Unit Notes ns +/- 250mV overdrive 10pF load ns Digital delay can max. of two 16MHz clock periods µs +/- 250mV overdrive No digital delay mV Programmable in 3 steps and zero V V µA µA ...
Page 74
... JN-DS-JN5148-001 1v7 Notes This is sensitive to the ESR of the crystal,Vdd and total capacitance at each pin Assuming xtal with ESR of less than 40kohms and CL= 9pF External caps = 15pF (Vdd/2mV pk-pk) see Appendix B Bondpad and package Total external capacitance ...
Page 75
... Unit 160 µA 24MHz +28% 24MHz +7% -0.015 %/°C 0.15 %/ Typ Max Unit ° -1.55 -1.66 mV/°C ±10 °C - °C - 2.5 855 mV 745 mV °C/LSB 0.182 0.209 JN-DS-JN5148-001 1v7 Notes Notes Includes absolute variation due to manufacturing & temp Typical at 3.0V 25° Vref ADC I/P Range 75 ...
Page 76
... Radio Transceiver This JN5148 meets all the requirements of the IEEE802.15.4 standard over 2.0 - 3.6V and offers the following improved RF characteristics. All RF characteristics are measured single ended. This part also meets the following regulatory body approvals, when used with Jennic’s Module Reference Designs. ...
Page 77
... Available through Hardware API Transmitter Characteristics +2.5 dBm - three 12dB steps (Note3) dBm Measured conducted into 50ohms <-70 30MHz to 1GHz, -40 1GHz to12.5GHz, The following exceptions apply 1.8 to 1.9GHz & 5.15 to 5.3GHz <-70 10 [2. maximum output power -38 -20 dBc At greater than 3.5MHz offset, as per 802.15.4, section 6.5.3.1 JN-DS-JN5148-001 1v7 Notes 77 ...
Page 78
... In three 12dB steps (Note3) dBm Measured conducted into 50ohms <-70 30MHz to 1GHz, -38 1GHz to12.5GHz, The following exceptions apply 1.8 to 1.9GHz & 5.15 to 5.3GHz <-70 9 [2. maximum output power -38 -20 dBc At greater than 3.5MHz offset, as per 802.15.4, section 6.5.3.1 JN-DS-JN5148-001 1v7 Notes © NXP Laboratories UK 2011 ...
Page 79
... Available through Hardware API Transmitter Characteristics +1.8 dBm - three 12dB steps (Note3) dBm Measured conducted into 50ohms <-70 30MHz to 1GHz, -42 1GHz to12.5GHz, The following exceptions apply 1.8 to 1.9GHz & 5.15 to 5.3GHz <-70 10 [2. maximum output power -38 -20 dBc At greater than 3.5MHz offset, as per 802.15.4, section 6.5.3.1 JN-DS-JN5148-001 1v7 Notes 79 ...
Page 80
... Note1: Blocker rejection is defined as the value, when 1% PER is seen with the wanted signal 3dB above sensitivity, as per 802.15.4 section 6.5.3.4 Note2: Channels 11,17,24 low/high values reversed. Note3 extra 2.5dB of attenuation is available if required. 80 JN-DS-JN5148-001 1v7 © NXP Laboratories UK 2011 ...
Page 81
... Appendix A Mechanical and Ordering Information A.1 56-pin QFN Package Drawing Figure 51: 56-pin QFN Package Drawings © NXP Laboratories UK 2011 JN-DS-JN5148-001 1v7 Controlling Dimension: mm millimetres Symbol Min. Nom. Max. A ------ ------ 0.9 A1 0.00 0.01 0.05 A2 ------ 0.65 0.7 A3 0.20 Ref. b 0.2 0.25 0.3 D 8.00 bsc D1 7.75 bsc D2 6.20 6.40 6.60 E 8.00 bsc E1 7.75 bsc E2 6.20 6.40 6.60 L 0.30 0.40 0.50 e 0.50 bsc υ1 0° ------ 12° ...
Page 82
... The following PCB decal is recommended; all dimensions are in millimetres (mm). The PCB schematic and layout rules detailed in Appendix B.4 must be followed. Failure will likely result in the JN5148 failing to meet the performance specification detailed herein and worst case may result in device not functioning in the end application. ...
Page 83
... A.3 Ordering Information The standard qualification for the JN5148 is Industrial temperature range: -40ºC to +85ºC, packaged in a 56-pin QFN package. Ordering Code Format: JN5148/XXX XXX: ROM Variant 001 Supports all available networking stacks Ordering Codes: Part Number Ordering Code JN5148-001 JN5148/001 The chip is available in three different reel quantities: • ...
Page 84
... A.4 Device Package Marking The diagram below shows the package markings for JN5148. The package on the left along with the legend information below it, shows the general format of package marking. The package on the right shows the specific markings for a JN5148-001 device, that came from assembly build number 1000135 and was manufactured week 12 of 2008 ...
Page 85
... Cumulative tolerance of 10 sprocket holes is ±0.20mm (II) (III) Measured from centreline of sprocket hole to centreline of pocket (IV) Other material available © NXP Laboratories UK 2011 Figure 54: Tape and Reel Orientation Dimensions (mm) 8.30 ±0. 8.30 ±0. 1.10 ±0. 7.50 ±0.10 F 12.00 ±0. 16.00 ±0.30 W Figure 55: Tape Dimensions JN-DS-JN5148-001 1v7 85 ...
Page 86
... High Impact Polystyrene, environmentally friendly, recyclable All dimensions and tolerances are fully compliant with EIA-481-B and are specified in millimetres. 6 window design with one window on each side blanked to allow adequate labelling space – 10e Ohms Square Figure 56: 180mm Reel Dimensions JN-DS-JN5148-001 1v7 © NXP Laboratories UK 2011 ...
Page 87
... C, and is dried before sealing in a moisture barrier bag (MBB) with desiccant bag weighing at 67.5 grams of activated clay and a humidity indicator card (HIC) meeting MIL-L-8835 specification. The MBB has a moisture-sensitivity caution label to indicate the moisture-sensitive classification of the enclosed devices. © NXP Laboratories UK 2011 9 11 – 10e Ohms Square Figure 57: 330mm Reel Dimensions JN-DS-JN5148-001 1v7 87 ...
Page 88
... Hence for a 9pF load capacitance, and a tight layout the external capacitors should be 15pF defines the oscillation frequency (series) m × JN-DS-JN5148-001 1v7 © NXP Laboratories UK 2011 ...
Page 89
... =40Ω, =1pF and JN-DS-JN5148-001 1v7 and C with C from the crystal C L × =18pF ( for a load 2.59mA/V. The JN5148 has square law ...
Page 90
... B.2 32MHz Oscillator The JN5148 contains the necessary on-chip components to build a 32 MHz reference oscillator with the addition of an external crystal resonator, two tuning capacitors. The schematic of these components are shown in Figure 57. The two capacitors, C1 and C2, will typically be 15pF ±5% and use a COG dielectric. For a detailed specification of the crystal required and factors affecting C1 and C2 see Appendix B ...
Page 91
... Circuit techniques have been used to apply compensation, such that the user need only design for nominal conditions. 4.35 4.3 4.25 4.2 4.15 4.1 -40 -20 4.31 4.3 4.29 4.28 2 2.2 2.4 © NXP Laboratories UK 2011 32MHz Crystal Oscillator Temperature (C) 32MHz Crystal Oscillator 2.6 2.8 3 Supply Voltage (VDD) JN-DS-JN5148-001 1v7 60 80 100 3.2 3.4 3.6 91 ...
Page 92
... B.3 32kHz Oscillator In order to obtain more accurate sleep periods, the JN5148 contains the necessary on-chip components to build an optional 32kHz oscillator with the addition of an external 32.768kHz crystal and two tuning capacitors. The crystal should be connected between XTAL32K_IN and XTAL32K_OUT (DIO9 and DIO10), with two equal capacitors to ground, one on each pin. The schematic of these components are shown in Figure 58. The two capacitors, C1 and C2, will typically be in the range 10 to 22pF ± ...
Page 93
... Crystal Oscillator Current 1.6 1.4 1.2 1 0.8 0 © NXP Laboratories UK 2011 Current Start-up Time 15pF 1.6uA 0.8Sec 9pF 1.4uA 0.6sec 22pF 2.4uA 1.1sec 2.8 3 3.2 Supply Voltage (VDD Crystal ESR (K ohm) JN-DS-JN5148-001 1v7 Max ESR 70KΩ 80KΩ 35KΩ 3.4 3.6 9pF 12.5pF ...
Page 94
... B.4 JN5148 Module Reference Designs For customers wishing to integrate the JN5148 device directly into their system, Jennic provide a range of Module Reference Designs, covering standard and high-power modules fitted with different Antennae To ensure the correct performance strongly recommended that where possible the design details provided by the reference designs, are used in their exact form for all end designs, this includes component values, pad dimensions, track layouts etc ...
Page 95
... L2 2.7nH Load Inductor MuRata LQP15MN2N7B02 Table 8: JN5148 Printed Antenna Reference Module Components and PCB Layout Constraints The paddle should be connected directly to ground. Any pads that requiring connection to ground should connecting directly to the paddle. © NXP Laboratories UK 2011 PCB Layout Constraints ...
Page 96
... The suggested reflow profile is shown in Figure 60. The specific paste manufacturers guidelines on peak flow temperature, soak times, time above liquidus and ramp rates should also be referenced. Figure 61: Recommended Reflow Profile for Lead-free Solder Paste or PPF lead frame 96 JN-DS-JN5148-001 1v7 © NXP Laboratories UK 2011 ...
Page 97
... JN-RD-6015 Standard Module Reference Design [7] JN-AN-1003 Boot Loader Operation RoHS Compliance JN5148 devices meet the requirements of Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS) and of the China RoHS (SJ/T11363 – 2006) requirements which st came into force on 1 March 2007 ...
Page 98
... April 2010 – Released as Production with revised Electrical Parameters section 1.5 14th September 2010 – Logo updated and support for JenNet added 1.6 24th November 2010 – Ordering information changed 1.7 5th May 2011 – Tape and reel information updated 98 JN-DS-JN5148-001 1v7 © NXP Laboratories UK 2011 ...
Page 99
... For the contact details of your local Jennic office or distributor, refer to the Jennic web site: © NXP Laboratories UK 2011 NXP Laboratories UK Ltd (Formerly Jennic Ltd) Furnival Street Sheffield S1 4QT United Kingdom Tel: +44 (0)114 281 2655 Fax: +44 (0) 114 281 2951 E-mail: info@jennic.com www.nxp.com/jennic JN-DS-JN5148-001 1v7 99 ...