EP4CE6E22C8LN Altera Corporation, EP4CE6E22C8LN Datasheet - Page 33

• Manufacturer Part Number: EP4CE6E22C8LN
• Description: IC CYCLONE IV FPGA 6K 144EQFP
• Manufacturer: Altera Corporation
• Series: CYCLONE® IV Er

Specifications of EP4CE6E22C8LN

• Number Of Logic Elements/cells: 6272
• Number Of Labs/clbs: 392
• Total Ram Bits: 276480
• Number Of I /o: 91
• Number Of Gates: -
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-LQFP Exposed Pad
• Lead Free Status: Lead free
• Rohs Status: RoHS Compliant

Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Table 1–36. LVDS Receiver Timing Specifications for Cyclone IV Devices
November 2011 Altera Corporation
SW
Input jitter
tolerance
t
Notes to
(1) Cyclone IV E—LVDS receiver is supported at all I/O Banks.
(2) t
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
LOCK
Symbol
Cyclone IV GX—LVDS receiver is supported at I/O Banks 3, 4, 5, 6, 7, 8, and 9.
C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
LOCK
(2)
Table
is the time required for the PLL to lock from the end-of-device configuration.
1–36:
f
Modes
—
—
—
External Memory Interface Specifications
The external memory interfaces for Cyclone IV devices are auto-calibrating and easy
to implement.
For more information about the supported maximum clock rate, device and pin
planning, IP implementation, and device termination, refer to
Performance Specifications
Table 1–37
Table 1–37. Memory Output Clock Jitter Specifications for Cyclone IV Devices
Preliminary
Clock period jitter
Cycle-to-cycle period jitter
Duty cycle jitter
Notes to
(1) Memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL
Min
—
—
—
standard.
output routed on a global clock (GCLK) network.
Table
C6
lists the memory output clock jitter specifications for Cyclone IV devices.
Max
400
500
Parameter
1
1–37:
Min
—
—
—
C7, I7
of the External Memory Interface Handbook.
Max
400
500
1
Min
—
—
—
C8, A7
Symbol
t
t
t
JIT(duty)
JIT(per)
JIT(cc)
Max
400
550
1
(1),
(3)
(Part 2 of 2)—Preliminary
Min
—
—
—
C8L, I8L
–125
–200
–150
Min
Max
550
600
1
Section III: System
Cyclone IV Device Handbook,
Max
125
200
150
Min
—
—
—
C9L
(1),
(2)
Max
640
700
—
1
Unit
ps
ps
ps
Volume 3
Unit
ms
ps
ps
1–33