EP4CGX110CF23I7N Altera Corporation, EP4CGX110CF23I7N Datasheet - Page 35

• Manufacturer Part Number: EP4CGX110CF23I7N
• Description: IC CYCLONE IV FPGA 110K 484FBGA
• Manufacturer: Altera Corporation
• Series: CYCLONE® IV GXr

Specifications of EP4CGX110CF23I7N

• Number Of Logic Elements/cells: 109424
• Number Of Labs/clbs: 6839
• Total Ram Bits: 5621760
• Number Of I /o: 270
• Number Of Gates: -
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-BGA
• Lead Free Status: Lead free
• Rohs Status: RoHS Compliant

Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Table 1–40. IOE Programmable Delay on Column Pins for Cyclone IV E 1.0 V Core Voltage Devices
Table 1–41. IOE Programmable Delay on Row Pins for Cyclone IV E 1.0 V Core Voltage Devices
Table 1–42. IOE Programmable Delay on Column Pins for Cyclone IV E 1.2 V Core Voltage Devices
Preliminary
November 2011 Altera Corporation
Input delay from
dual-purpose clock pin to
fan-out destinations
Notes to
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
Input delay from pin to
internal cells
Input delay from pin to
input register
Delay from output register
to output pin
Input delay from
dual-purpose clock pin to
fan-out destinations
Notes to
(1) The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Quartus II software.
Input delay from pin to
internal cells
Input delay from pin to
input register
Delay from output
register to output pin
(Part 2 of 2)—Preliminary
Parameter
Table
Table
Parameter
Parameter
1–40:
1–41:
Table 1–42
core voltage devices.
Pad to I/O
dataout to
core
Pad to I/O
input register
I/O output
register to
pad
Affected
Paths
Pad to global
clock network
Pad to I/O
dataout to core
Pad to I/O input
register
I/O output
register to pad
Pad to global
clock network
Paths Affected
Paths Affected
and
Table 1–43
Number
Setting
of
7
8
2
Number
Number
Setting
Setting
Offset
12
12
of
of
7
8
2
Min
list the IOE programmable delay for Cyclone IV E 1.2 V
0
0
0
1.314 1.211 1.211 2.177 2.340 2.433 2.388 2.508
1.307 1.203 1.203
0.437 0.402 0.402 0.747 0.820 0.880 0.834 0.873
Offset
Offset
Min
Min
C6
0
0
0
0
0
Fast Corner
I7
2.057
2.059
0.670
0.960
0.971
C8L
C8L
Fast Corner
Fast Corner
A7
0.931
1.921
1.919
0.623
0.919
I8L
I8L
2.19
Max Offset
C6
Max Offset
Max Offset
1.684
3.389
3.420
1.160
1.656
C8L
C8L
2.387 2.540 2.430 2.545
C7
Slow Corner
Slow Corner
(1),
Slow Corner
Cyclone IV Device Handbook,
2.298
4.146
4.374
1.420
2.258
C9L
C9L
(1),
(1),
(2)
C8
—Preliminary
(2)
(2)
(Part 1 of 2)—
1.684
1.656
3.412
3.441
1.168
I8L
I8L
I7
Volume 3
Unit
Unit
A7
ns
ns
ns
ns
ns
1–35
Unit
ns
ns
ns